138 lines
5.2 KiB
C++
138 lines
5.2 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2023 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <wx/string.h>
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#include <font/fontconfig.h>
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#include <pcb_io_solidworks.h>
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#include <pcb_io_altium_designer.h>
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#include <altium_pcb.h>
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#include <io/altium/altium_binary_parser.h>
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#include <pcb_io/pcb_io.h>
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#include <reporter.h>
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#include <board.h>
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#include <compoundfilereader.h>
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#include <utf.h>
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PCB_IO_SOLIDWORKS::PCB_IO_SOLIDWORKS() : PCB_IO( wxS( "Solidworks PCB" ) )
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{
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m_reporter = &WXLOG_REPORTER::GetInstance();
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RegisterLayerMappingCallback( PCB_IO_ALTIUM_DESIGNER::DefaultLayerMappingCallback );
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}
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PCB_IO_SOLIDWORKS::~PCB_IO_SOLIDWORKS()
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{
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}
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bool PCB_IO_SOLIDWORKS::CanReadBoard( const wxString& aFileName ) const
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{
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if( !PCB_IO::CanReadBoard( aFileName ) )
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return false;
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return PCB_IO_ALTIUM_DESIGNER::checkFileHeader( aFileName );
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}
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BOARD* PCB_IO_SOLIDWORKS::LoadBoard( const wxString& aFileName, BOARD* aAppendToMe,
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const STRING_UTF8_MAP* aProperties, PROJECT* aProject )
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{
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m_props = aProperties;
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m_board = aAppendToMe ? aAppendToMe : new BOARD();
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fontconfig::FONTCONFIG::SetReporter( &WXLOG_REPORTER::GetInstance() );
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// Give the filename to the board if it's new
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if( !aAppendToMe )
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m_board->SetFileName( aFileName );
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// clang-format off
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const std::map<ALTIUM_PCB_DIR, std::string> mapping = {
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{ ALTIUM_PCB_DIR::FILE_HEADER, "FileHeader" },
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{ ALTIUM_PCB_DIR::ARCS6, "D2864697BB2D411B857EBD69D74447" },
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{ ALTIUM_PCB_DIR::BOARD6, "21CE7E3D9BFF41679BACA1184CAF54" },
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{ ALTIUM_PCB_DIR::BOARDREGIONS, "67075A4119214CE4AB174F9B1A9A41" },
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{ ALTIUM_PCB_DIR::CLASSES6, "1122D4F14A924F9CA5C2060AF370E0" },
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{ ALTIUM_PCB_DIR::COMPONENTS6, "208CAE8E44BD43D5B3CCA426D9331B" },
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{ ALTIUM_PCB_DIR::COMPONENTBODIES6, "6DDF94E6CB364893BED31C189F9AF3" },
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{ ALTIUM_PCB_DIR::DIMENSIONS6, "6148AE8C77B042798B46830E96BB24" },
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{ ALTIUM_PCB_DIR::FILLS6, "5944DE0E258C41E2B0B382AC964048" },
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{ ALTIUM_PCB_DIR::MODELS, "874F98A7E25A48EDAD394EB891E503" },
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{ ALTIUM_PCB_DIR::NETS6, "0201837ACD434D55B34BBC68B75BAB" },
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{ ALTIUM_PCB_DIR::PADS6, "E4D0C33E25824886ABC7FEEAE7B521" },
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{ ALTIUM_PCB_DIR::POLYGONS6, "7ABD4252549749DD8DB16804819AC3" },
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{ ALTIUM_PCB_DIR::REGIONS6, "6B3892541AB94CD999291D590B5C86" }, // probably wrong; in as a placeholder
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{ ALTIUM_PCB_DIR::RULES6, "7009830ADF65423FA6CCB73A77E710" },
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{ ALTIUM_PCB_DIR::SHAPEBASEDREGIONS6, "91241C66300E4490965070BA56F6F7" },
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{ ALTIUM_PCB_DIR::TEXTS6, "4AF3D139533041489C2A57BBF9890D" },
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{ ALTIUM_PCB_DIR::TRACKS6, "5D0C6E18E16A4BBFAA256C24B79EAE" },
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{ ALTIUM_PCB_DIR::VIAS6, "2AF5387F097242D3A1095B6FAC3397" },
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{ ALTIUM_PCB_DIR::WIDESTRINGS6, "9B378679AF85466C8673A41EE46393" }
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/*
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* Understood but not needed:
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* 04A8F96E0E4C478C813AE57CACCD0F - Legacy text storage
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* 01F1BD1AA06E4D6A9D1ABF0BBFF4A4 - Fwd/Back compatibility messages
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*
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* Not yet used by KiCad:
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* 7C01505E39124E67BCCAB1883B8FB7 - Design Rule Checker Options6
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* 63B31A3709B54882BFA96424906BE8 - EmbeddedFonts6
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* 8B83C7E94C1D419B9B2D5505479820 - Pin Swap Options6
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* F78C10230A794F5C93ACB50AC693B2 - Advanced Placer Options6
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*
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* No data yet on:
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* 1C0DB1ED572645BEB65D029D20406C
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* 2AA5C1C72BF14315A47DD931B84A79
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* 6468C28D32CC4867AB374091CC8431
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* 6B3892541AB94CD999291D590B5C86
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* 8675F4105E444E6D9B2BEE6273769D
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* B983FCC2B6DE46E0B94006B6393235
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* D6551D22B6DB44659C3F32F7E1949D
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*
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* Not yet identified:
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* D06DD2E4A51C4A3EA96D9ED8C8F3F3
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* F9C465994DE840579ED19E820C19C2
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*
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* Region-like objects that don't map cleanly (maybe Solidworks sketches?)
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* 84958494F3F54075975C4E199DB8EB
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* 2E731D36D1F049428744F0661F3E44
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*/
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};
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// clang-format on
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ALTIUM_COMPOUND_FILE altiumPcbFile( aFileName );
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try
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{
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// Parse File
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ALTIUM_PCB pcb( m_board, m_progressReporter, m_layer_mapping_handler, m_reporter );
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pcb.Parse( altiumPcbFile, mapping );
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}
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catch( CFB::CFBException& exception )
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{
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THROW_IO_ERROR( exception.what() );
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}
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return m_board;
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}
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