Seth Hillbrand 890376d04f Do not use cache when we modify vertices ... When we add vertices to the tesselation routines, we cannot reuse these without the original vertex points. It may be possible to copy and modify the vertices from the hint data so that they are properly positioned but naive attempts (moving based on first point) did not work, so for now, we disable the hint cache when the vertex sizes do not match as this prevents OOB access Fixes https://gitlab.com/kicad/code/kicad/-/issues/17621 (cherry picked from commit 06b199fd41)		2024-03-31 15:01:16 -07:00
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data	Update triangulation to handle poly-intersection	2024-03-28 13:55:06 -07:00
mocks	Schematic parity checking for CLI DRC.	2024-02-02 23:05:37 +00:00
pcbnew_utils	Use 'uuid' (not 'id') in the s-expr PCB groups/generator format	2023-12-31 23:09:26 +00:00
qa_utils	Schematic parity checking for CLI DRC.	2024-02-02 23:05:37 +00:00
resources/linux	Fix source comment / documentation typos	2021-06-09 19:32:58 +00:00
schematic_utils	Introduce base IO_MGR class and unify RELEASER objects	2023-12-29 00:37:38 +00:00
tests	Do not use cache when we modify vertices	2024-03-31 15:01:16 -07:00
tools	pns_debug_tool: Fix "save as" to save log file with new router state	2024-02-12 21:22:57 +01:00
CMakeLists.txt	Move tests around	2023-04-24 22:09:36 -04:00