359 lines
6.6 KiB
INI
359 lines
6.6 KiB
INI
update=03/06/2020 18:35:28
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version=1
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last_client=kicad
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[common]
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NetDir=
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[general]
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version=1
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RootSch=interf_u.sch
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BoardNm=interf_u.brd
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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[eeschema]
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version=1
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LibDir=
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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NetFmtName=
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SpiceAjustPassiveValues=0
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SubpartIdSeparator=0
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SubpartFirstId=65
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LabSize=50
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TextOffsetRatio=0.1
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LineThickness=6
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BusThickness=12
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WireThickness=6
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PinSymbolSize=25
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JunctionSize=32
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FieldNameTemplates=(templatefields)
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ERC_TestSimilarLabels=1
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ERC_CheckUniqueGlobalLabels=1
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ERC_CheckBusDriverConflicts=1
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ERC_CheckBusEntryConflicts=1
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ERC_CheckBusToBusConflicts=1
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ERC_CheckBusToNetConflicts=1
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[sheetnames]
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1=c41dc74b-8443-4c5f-8f8b-b1059e0fb71f:
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[pcbnew]
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version=1
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PageLayoutDescrFile=pagelayout_logo.kicad_wks
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LastNetListRead=interf_u.net
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LastSTEPExportPath=
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LastIDFExportPath=
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LastVRMLExportPath=
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LastSpecctraDSNExportPath=
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LastGenCADExportPath=
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CopperLayerCount=2
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BoardThickness=1.6002
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AllowMicroVias=0
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AllowBlindVias=0
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MinClearance=0.2
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MinTrackWidth=0.2
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MinViaAnnulus=0.05
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MinViaDiameter=0.8999999999999999
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MinThroughDrill=0.5
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MinMicroViaDiameter=0.5
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MinMicroViaDrill=0.127
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MinHoleToHole=0.25
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Unconnected_items=error
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Track_too_close_to_hole=error
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Track_too_close_to_pad=error
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Track_too_close_to_via=error
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Track_too_close_to_copper_area=error
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Track_too_close_to_copper_item=error
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Vias_too_close=error
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Via_too_close_to_track=error
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Via_too_close_to_copper_item=error
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Track_ends_too_close=error
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Parallel_tracks_too_close=error
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Tracks_crossing=error
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Track_too_close_to_board_edge=error
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Via_too_close_to_board_edge=error
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Pad_too_close_to_board_edge=error
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Pads_too_close=error
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Pad_too_close_to_copper_item=error
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Copper_areas_intersect=error
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Copper_areas_too_close=error
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Copper_zone_net_has_no_pads=error
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Via_is_not_connected=warning
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Track_has_unconnected_end=warning
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Hole_too_close_to_pad=error
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Hole_too_close_to_track=error
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Drilled_holes_too_close_together=error
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Track_width_too_small=error
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Track_width_too_large=error
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Via_size_too_small=error
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Via_annulus_too_small=error
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Via_drill_too_small=error
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Pad_drill_too_small=error
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Via_hole_larger_than_diameter=error
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Micro_via_not_allowed=error
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Micro_via_through_too_many_layers=error
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Micro_via_size_too_small=error
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Micro_via_drill_too_small=error
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Buried_via_not_allowed=error
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NetClass_Track_Width_too_small=error
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NetClass_Clearance_too_small=error
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NetClass_via_annulus_too_small=error
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NetClass_Via_Dia_too_small=error
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NetClass_Via_Drill_too_small=error
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NetClass_uVia_Dia_too_small=error
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NetClass_uVia_Drill_too_small=error
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Via_inside_keepout_area=error
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Micro_via_inside_keepout_area=error
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Buried_via_inside_keepout_area=error
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Track_inside_keepout_area=error
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Pad_inside_keepout_area=error
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Footprint_inside_keepout_area=error
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Hole_inside_keepout_area=error
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Text_inside_keepout_area=error
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Graphic_inside_keepout_area=error
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Courtyards_overlap=error
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Footprint_has_no_courtyard_defined=ignore
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Footprint_has_malformed_courtyard=error
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PTH_inside_courtyard=ignore
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NPTH_inside_courtyard=ignore
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Item_on_a_disabled_layer=error
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Board_has_malformed_outline=error
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Missing_footprint=warning
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Duplicate_footprints=warning
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Extra_footprint=warning
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Unresolved_text_variable=error
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CopperEdgeClearance=0
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TrackWidth1=0.4
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TrackWidth2=0.381
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TrackWidth3=0.762
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ViaDiameter1=1.4
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ViaDrill1=0.6
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ViaDiameter2=1.524
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ViaDrill2=0.762
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.381
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SilkTextSizeV=1.524
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SilkTextSizeH=1.524
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SilkTextSizeThickness=0.3048
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SilkTextItalic=0
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SilkTextUpright=0
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CopperLineWidth=0.381
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CopperTextSizeV=2.032
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CopperTextSizeH=1.524
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=0
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EdgeCutLineWidth=0.127
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CourtyardLineWidth=0.05
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FabLineWidth=0.09999999999999999
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FabTextSizeV=1
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FabTextSizeH=1
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FabTextSizeThickness=0.15
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FabTextItalic=0
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FabTextUpright=0
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OthersLineWidth=0.09999999999999999
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=0
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DimensionUnits=0
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DimensionPrecision=1
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SolderMaskClearance=0.05
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=top_copper
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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Name=bottom_copper
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Type=0
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Enabled=1
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[pcbnew/Layer.B.Adhes]
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Enabled=1
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[pcbnew/Layer.F.Adhes]
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Enabled=1
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[pcbnew/Layer.B.Paste]
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Enabled=1
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[pcbnew/Layer.F.Paste]
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Enabled=1
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[pcbnew/Layer.B.SilkS]
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Enabled=1
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[pcbnew/Layer.F.SilkS]
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Enabled=1
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[pcbnew/Layer.B.Mask]
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Enabled=1
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[pcbnew/Layer.F.Mask]
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Enabled=1
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[pcbnew/Layer.Dwgs.User]
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Enabled=1
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[pcbnew/Layer.Cmts.User]
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Enabled=1
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[pcbnew/Layer.Eco1.User]
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Enabled=1
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[pcbnew/Layer.Eco2.User]
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Enabled=1
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[pcbnew/Layer.Edge.Cuts]
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Enabled=1
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[pcbnew/Layer.Margin]
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Enabled=1
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[pcbnew/Layer.B.CrtYd]
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Enabled=1
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[pcbnew/Layer.F.CrtYd]
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Enabled=1
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[pcbnew/Layer.B.Fab]
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Enabled=1
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[pcbnew/Layer.F.Fab]
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Enabled=1
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[pcbnew/Layer.Rescue]
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Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.254
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TrackWidth=0.4
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ViaDiameter=1.4
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ViaDrill=0.6
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uViaDiameter=0.5
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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Name=Power
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Clearance=0.254
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TrackWidth=0.5
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ViaDiameter=1.6
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ViaDrill=0.6
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uViaDiameter=0.5
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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