282 lines
8.2 KiB
C++
282 lines
8.2 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2007-2014 Jean-Pierre Charras, jp.charras at wanadoo.fr
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @file ratsnest.cpp
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* @brief Ratsnets functions.
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*/
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#include <fctsys.h>
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#include <gr_basic.h>
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#include <common.h>
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#include <class_drawpanel.h>
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#include <pcb_edit_frame.h>
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#include <macros.h>
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#include <class_board.h>
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#include <class_module.h>
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#include <class_track.h>
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#include <pcbnew.h>
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#include <connectivity_data.h>
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#include <ratsnest_data.h>
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/**
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* Function Compile_Ratsnest
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* Create the entire board ratsnest.
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* Must be called after a board change (changes for
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* pads, footprints or a read netlist ).
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* @param aDC = the current device context (can be NULL)
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* @param aDisplayStatus : if true, display the computation results
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*/
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void PCB_BASE_FRAME::Compile_Ratsnest( wxDC* aDC, bool aDisplayStatus )
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{
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GetBoard()->GetConnectivity()->RecalculateRatsnest();
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GetBoard()->m_Status_Pcb = 0; // we want a full ratsnest computation, from the scratch
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if( GetBoard()->IsElementVisible( LAYER_RATSNEST ) && aDC )
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DrawGeneralRatsnest( aDC, 0 );
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wxString msg;
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ClearMsgPanel();
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if( aDisplayStatus )
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{
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std::shared_ptr<CONNECTIVITY_DATA> conn = m_Pcb->GetConnectivity();
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msg.Printf( wxT( " %d" ), conn->GetPadCount() );
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AppendMsgPanel( wxT( "Pads" ), msg, RED );
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msg.Printf( wxT( " %d" ), conn->GetNetCount() - 1 /* Don't include "No Net" in count */ );
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AppendMsgPanel( wxT( "Nets" ), msg, CYAN );
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SetMsgPanel( m_Pcb );
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}
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}
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/**
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* function DrawGeneralRatsnest
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* Only ratsnest items with the status bit CH_VISIBLE set are displayed
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* @param aDC = the current device context (can be NULL)
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* @param aNetcode: if > 0, Display only the ratsnest relative to the
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* corresponding net_code
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*/
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void PCB_BASE_FRAME::DrawGeneralRatsnest( wxDC* aDC, int aNetcode )
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{
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if( ( m_Pcb->m_Status_Pcb & DO_NOT_SHOW_GENERAL_RASTNEST ) )
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{
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return;
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}
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if( aDC == NULL )
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return;
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auto connectivity = m_Pcb->GetConnectivity();
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if( !connectivity->TryLock() )
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return;
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COLOR4D color = Settings().Colors().GetItemColor( LAYER_RATSNEST );
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for( int i = 1 /* skip "No Net" at [0] */; i < connectivity->GetNetCount(); ++i )
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{
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RN_NET* net = connectivity->GetRatsnestForNet( i );
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if( !net )
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continue;
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if( ( aNetcode <= 0 ) || ( aNetcode == i ) )
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{
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for( const auto& edge : net->GetEdges() )
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{
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auto s = edge.GetSourcePos();
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auto d = edge.GetTargetPos();
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auto sn = edge.GetSourceNode();
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auto dn = edge.GetTargetNode();
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if( !sn->Valid() || !dn->Valid() )
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continue;
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bool enable = !sn->GetNoLine() && !dn->GetNoLine();
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bool show = sn->Parent()->GetLocalRatsnestVisible()
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|| dn->Parent()->GetLocalRatsnestVisible();
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if( enable && show )
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GRLine( m_canvas->GetClipBox(), aDC, wxPoint( s.x, s.y ), wxPoint( d.x,
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d.y ), 0, color );
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}
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}
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}
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connectivity->Unlock();
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}
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void PCB_BASE_FRAME::TraceModuleRatsNest( wxDC* DC )
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{
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if( DC == NULL )
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return;
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COLOR4D tmpcolor = Settings().Colors().GetItemColor( LAYER_RATSNEST );
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for( const auto& l : GetBoard()->GetConnectivity()->GetDynamicRatsnest() )
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{
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GRLine( m_canvas->GetClipBox(), DC, wxPoint( l.a.x, l.a.y ), wxPoint( l.b.x,
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l.b.y ), 0, tmpcolor );
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}
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}
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/*
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* PCB_BASE_FRAME::BuildAirWiresTargetsList and
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* PCB_BASE_FRAME::TraceAirWiresToTargets
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* are 2 function to show the near connecting points when
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* a new track is created, by displaying g_MaxLinksShowed airwires
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* between the on grid mouse cursor and these connecting points
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* during the creation of a track
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*/
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/* Buffer to store pads coordinates when creating a track.
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* these pads are members of the net
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* and when the mouse is moved, the g_MaxLinksShowed links to neighbors are
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* drawn
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*/
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static wxPoint s_CursorPos; // Coordinate of the moving point (mouse cursor and
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// end of current track segment)
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/* Function BuildAirWiresTargetsList
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* Build a list of candidates that can be a coonection point
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* when a track is started.
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* This functions prepares data to show airwires to nearest connecting points (pads)
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* from the current new track to candidates during track creation
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*/
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static BOARD_CONNECTED_ITEM* s_ref = nullptr;
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static int s_refNet = -1;
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void PCB_BASE_FRAME::BuildAirWiresTargetsList( BOARD_CONNECTED_ITEM* aItemRef,
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const wxPoint& aPosition, int aNet )
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{
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s_CursorPos = aPosition; // needed for sort_by_distance
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s_ref = aItemRef;
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s_refNet = aNet;
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}
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static MODULE movedModule( nullptr );
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void PCB_BASE_FRAME::build_ratsnest_module( MODULE* aModule, wxPoint aMoveVector )
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{
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auto connectivity = GetBoard()->GetConnectivity();
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movedModule = *aModule;
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movedModule.Move( -aMoveVector );
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connectivity->ClearDynamicRatsnest();
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connectivity->BlockRatsnestItems( { aModule } );
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connectivity->ComputeDynamicRatsnest( { &movedModule } );
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}
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void PCB_BASE_FRAME::TraceAirWiresToTargets( wxDC* aDC )
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{
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auto connectivity = GetBoard()->GetConnectivity();
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auto displ_opts = (PCB_DISPLAY_OPTIONS*) GetDisplayOptions();
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auto targets = connectivity->NearestUnconnectedTargets( s_ref, s_CursorPos, s_refNet );
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if( aDC == NULL )
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return;
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GRSetDrawMode( aDC, GR_XOR );
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for( int i = 0; i < std::min( (int) displ_opts->m_MaxLinksShowed, (int) targets.size() ); i++ )
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{
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auto p = targets[i];
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GRLine( m_canvas->GetClipBox(), aDC, s_CursorPos, wxPoint( p.x, p.y ), 0, YELLOW );
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}
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}
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// Redraw in XOR mode the outlines of the module.
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void MODULE::DrawOutlinesWhenMoving( EDA_DRAW_PANEL* panel, wxDC* DC,
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const wxPoint& aMoveVector )
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{
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int pad_fill_tmp;
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D_PAD* pt_pad;
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DrawEdgesOnly( panel, DC, aMoveVector, GR_XOR );
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auto displ_opts = (PCB_DISPLAY_OPTIONS*) ( panel->GetDisplayOptions() );
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// Show pads in sketch mode to speedu up drawings
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pad_fill_tmp = displ_opts->m_DisplayPadFill;
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displ_opts->m_DisplayPadFill = true;
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pt_pad = PadsList();
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for( ; pt_pad != NULL; pt_pad = pt_pad->Next() )
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pt_pad->Draw( panel, DC, GR_XOR, aMoveVector );
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displ_opts->m_DisplayPadFill = pad_fill_tmp;
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if( displ_opts->m_Show_Module_Ratsnest )
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{
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PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) panel->GetParent();
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frame->build_ratsnest_module( this, aMoveVector );
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frame->TraceModuleRatsNest( DC );
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}
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}
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void PCB_EDIT_FRAME::Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC )
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{
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if( item && item->Type() == PCB_MODULE_T )
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{
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auto mod = static_cast<MODULE*> (item);
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for( auto pad : mod->Pads() )
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{
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pad->SetLocalRatsnestVisible( !pad->GetLocalRatsnestVisible() );
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}
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}
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else
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{
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auto modules = GetBoard()->Modules();
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for( auto mod : modules )
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{
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for( auto pad : mod->Pads() )
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{
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pad->SetLocalRatsnestVisible( false );
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}
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}
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}
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m_canvas->Refresh();
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}
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