563 lines
18 KiB
C++
563 lines
18 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
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* Author: Seth Hillbrand <seth@kipro-pcb.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef PCBNEW_IMPORTERS_IMPORT_FABMASTER_H_
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#define PCBNEW_IMPORTERS_IMPORT_FABMASTER_H_
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#include <eda_text.h>
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#include <geometry/shape_arc.h>
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#include <hash_eda.h>
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#include <pad_shapes.h>
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#include <deque>
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#include <functional>
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#include <iostream>
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#include <map>
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#include <memory>
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#include <set>
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#include <unordered_map>
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#include <string>
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#include <vector>
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#include <wx/filename.h>
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enum PCB_LAYER_ID : int;
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class BOARD;
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class FABMASTER
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{
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public:
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using single_row = std::vector<std::string>;
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FABMASTER() :
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has_pads( false ), has_comps( false ), has_graphic( false ),
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has_nets( false ), has_pins( false )
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{}
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bool Read( const std::string& aFile );
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bool Process();
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bool LoadBoard( BOARD* aBoard );
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private:
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wxFileName m_filename;
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enum section_type : int
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{
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UNKNOWN_EXTRACT,
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EXTRACT_PADSTACKS,
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EXTRACT_PAD_SHAPES,
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EXTRACT_FULL_LAYERS,
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EXTRACT_VIAS,
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FABMASTER_EXTRACT_PINS,
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EXTRACT_PINS,
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EXTRACT_TRACES,
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EXTRACT_GRAPHICS,
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EXTRACT_BASIC_LAYERS,
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EXTRACT_NETS,
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EXTRACT_REFDES
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};
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std::deque<single_row> rows;
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bool has_pads;
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bool has_comps;
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bool has_graphic;
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bool has_nets;
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bool has_pins;
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struct FM_PAD
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{
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std::string name;
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bool fixed;
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bool via;
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PAD_SHAPE_T shape;
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std::string custom_name;
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bool top;
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bool bottom;
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bool paste;
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bool mask;
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bool drill;
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bool plated;
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bool is_octogon;
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int drill_size_x;
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int drill_size_y;
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int width;
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int height;
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int mask_width;
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int mask_height;
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int paste_width;
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int paste_height;
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int x_offset;
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int y_offset;
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int antipad_size;
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struct HASH
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{
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std::size_t operator()( const FM_PAD& aPad ) const
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{
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return std::hash<std::string>{}( aPad.name );
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}
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};
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};
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std::unordered_map<std::string, FM_PAD> pads;
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enum COMPCLASS
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{
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COMPCLASS_NONE,
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COMPCLASS_IO,
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COMPCLASS_IC,
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COMPCLASS_DISCRETE
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};
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enum SYMTYPE
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{
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SYMTYPE_NONE,
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SYMTYPE_PACKAGE,
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SYMTYPE_MECH,
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SYMTYPE_FORMAT,
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SYMTYPE_DRAFTING
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};
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// A!NET_NAME!REFDES!PIN_NUMBER!PIN_NAME!PIN_GROUND!PIN_POWER!
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struct NETNAME
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{
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std::string name; ///!< NET_NAME
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std::string refdes; ///!< REFDES
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std::string pin_num; ///!< PIN_NUMBER
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std::string pin_name; ///!< PIN_NAME
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bool pin_gnd; ///!< PIN_GND
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bool pin_pwr; ///!< PIN_PWR
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struct LESS
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{
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bool operator()(const NETNAME& lhs, const NETNAME& rhs) const
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{
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if( lhs.refdes == rhs.refdes )
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return lhs.pin_num < rhs.pin_num;
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return lhs.refdes < rhs.refdes;
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}
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};
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};
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std::map<std::pair<std::string, std::string>, NETNAME> pin_nets;
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std::set<std::string> netnames;
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struct CLASS
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{
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std::string name; ///!< CLASS
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std::string subclass; ///!< SUBCLASS
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};
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enum GRAPHIC_SHAPE
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{
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GR_SHAPE_LINE,
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GR_SHAPE_TEXT,
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GR_SHAPE_RECTANGLE,
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GR_SHAPE_ARC
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};
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enum GRAPHIC_TYPE
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{
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GR_TYPE_NONE,
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GR_TYPE_CONNECT,
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GR_TYPE_NOTCONNECT,
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GR_TYPE_SHAPE,
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GR_TYPE_POLYGON,
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GR_TYPE_VOID
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};
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struct GRAPHIC_ITEM
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{
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int start_x; ///<! GRAPHIC_DATA_1
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int start_y; ///<! GRAPHIC_DATA_2
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int width; ///<! Various sections depending on type
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std::string layer; ///<! SUBCLASS
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std::string symbol; ///<! SYMBOL
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std::string refdes; ///<! REFDES
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int seq; ///<! RECORD_TAG[0]
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int subseq; ///<! RECORD_TAG[1]
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GRAPHIC_TYPE type; ///<! Type of graphic item
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GRAPHIC_SHAPE shape; ///<! Shape of the graphic_item
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struct SEQ_CMP
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{
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bool operator()(const std::unique_ptr<GRAPHIC_ITEM>& lhs,
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const std::unique_ptr<GRAPHIC_ITEM>& rhs) const
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{
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return lhs->seq < rhs->seq;
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}
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};
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};
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struct GRAPHIC_LINE : public GRAPHIC_ITEM
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{
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int end_x; ///<! GRAPHIC_DATA_3
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int end_y; ///<! GRAPHIC_DATA_4
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///<! width is GRAPHIC_DATA_5
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};
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struct GRAPHIC_ARC : public GRAPHIC_ITEM
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{
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int end_x; ///<! GRAPHIC_DATA_3
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int end_y; ///<! GRAPHIC_DATA_4
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int center_x; ///<! GRAPHIC_DATA_5
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int center_y; ///<! GRAPHIC_DATA_6
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int radius; ///<! GRAPHIC_DATA_7
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///<! width is GRAPHIC_DATA_8
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bool clockwise; ///<! GRAPHIC_DATA_9
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SHAPE_ARC result; ///<! KiCad-style arc representation
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};
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struct GRAPHIC_RECTANGLE : public GRAPHIC_ITEM
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{
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int end_x; ///<! GRAPHIC_DATA_3
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int end_y; ///<! GRAPHIC_DATA_4
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bool fill; ///<! GRAPHIC_DATA_5
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};
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struct GRAPHIC_TEXT : public GRAPHIC_ITEM
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{
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double rotation; ///<! GRAPHIC_DATA_3
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bool mirror; ///<! GRAPHIC_DATA_4
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EDA_TEXT_HJUSTIFY_T orient; ///<! GRAPHIC_DATA_5
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// GRAPHIC_DATA_6 is
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// SIZE FONT HEIGHT WIDTH ITAL LINESPACE THICKNESS
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int height; ///<! GRAPHIC_DATA_6[2]
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int thickness; ///<! GRAPHIC_DATA_6[6]
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bool ital; ///<! GRAPHIC_DATA_6[4] != 0.0
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std::string text; ///<! GRAPHIC_DATA_7
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};
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using graphic_element = std::set<std::unique_ptr<GRAPHIC_ITEM>, GRAPHIC_ITEM::SEQ_CMP>;
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/// A!LAYER_SORT!LAYER_SUBCLASS!LAYER_ARTWORK!LAYER_USE!LAYER_CONDUCTOR!LAYER_DIELECTRIC_CONSTANT
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/// !LAYER_ELECTRICAL_CONDUCTIVITY!LAYER_MATERIAL!LAYER_SHIELD_LAYER!LAYER_THERMAL_CONDUCTIVITY!LAYER_THICKNESS!
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struct FABMASTER_LAYER
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{
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int id; ///<! LAYER_SORT
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std::string name; ///<! LAYER_SUBCLASS
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bool positive; ///<! LAYER_ARTWORK (either POSITIVE or NEGATIVE)
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std::string use; ///<! LAYER_USE
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bool conductive; ///<! LAYER_CONDUCTOR
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double er; ///<! LAYER_DIELECTRIC_CONSTANT
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double conductivity; ///<! LAYER_ELECTRICAL_CONDUCTIVITY
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std::string material; ///<! LAYER_MATERIAL
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bool shield; ///<! LAYER_SHIELD_LAYER
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double thermal_cond; ///<! LAYER_THERMAL_CONDUCTIVITY
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double thickness; ///<! LAYER_THICKNESS
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int layerid; ///<! pcbnew layer (assigned)
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bool disable; ///<! if true, prevent the layer elements from being used
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struct BY_ID
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{
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bool operator()(const FABMASTER_LAYER* lhs, const FABMASTER_LAYER* rhs) const
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{
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return lhs->id < rhs->id;
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}
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};
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};
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std::map<std::string, FABMASTER_LAYER> layers;
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/**
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* A!SUBCLASS!PAD_SHAPE_NAME!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!RECORD_TAG!GRAPHIC_DATA_1!
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* GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!
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* GRAPHIC_DATA_8!GRAPHIC_DATA_9!PAD_STACK_NAME!REFDES!PIN_NUMBER!
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*/
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struct PAD_SHAPE
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{
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std::string name; ///<! PAD_SHAPE_NAME
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std::string padstack; ///<! PAD_STACK_NAME
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std::string refdes; ///<! REFDES
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std::string pinnum; ///<! PIN_NUMBER
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std::map<int, graphic_element> elements;
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struct HASH
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{
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std::size_t operator()( const std::unique_ptr<PAD_SHAPE>& aPad ) const
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{
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return std::hash<std::string>{}( aPad->name );
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}
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};
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};
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std::unordered_map<std::string, PAD_SHAPE> pad_shapes;
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// * A!SYM_TYPE!SYM_NAME!REFDES!SYM_X!SYM_Y!SYM_ROTATE!SYM_MIRROR!NET_NAME!CLASS!SUBCLASS!RECORD_TAG!
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// * GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!
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// * GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!COMP_DEVICE_TYPE!
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// * COMP_PACKAGE!COMP_PART_NUMBER!COMP_VALUE!CLIP_DRAWING!
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struct SYMBOL
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{
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int sym_id; ///<! RECORD_TAG[0]
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int seq_id; ///<! RECORD_TAG[1] (RECORD_TAG is of the form "x y z")
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int subseq_id; ///<! RECORD_TAG[2] (RECORD_TAG is of the form "x y z")
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std::string name; ///<! SYM_NAME
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std::string refdes; ///<! REFDES
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int x; ///<! SYM_X
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int y; ///<! SYM_Y
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std::map<int, graphic_element> elements;
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struct HASH
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{
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std::size_t operator()( const FABMASTER::SYMBOL& aSym ) const
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{
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return std::hash<std::string>{}( aSym.name );
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}
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};
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};
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// Temporary data structure to pass graphic data from file for processing
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struct GRAPHIC_DATA
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{
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std::string graphic_dataname;
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std::string graphic_datanum;
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std::string graphic_data1;
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std::string graphic_data2;
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std::string graphic_data3;
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std::string graphic_data4;
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std::string graphic_data5;
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std::string graphic_data6;
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std::string graphic_data7;
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std::string graphic_data8;
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std::string graphic_data9;
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std::string graphic_data10;
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};
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std::unordered_map<std::string, SYMBOL> symbols;
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// * A!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!RECORD_TAG!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!
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// * GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!
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// * SUBCLASS!SYM_NAME!REFDES!
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struct GEOM_GRAPHIC
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{
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std::string subclass; ///<! SUBCLASS
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std::string name; ///<! SYM_NAME
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std::string refdes; ///<! REFDES
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int id; ///<! RECORD_TAG[0]
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std::unique_ptr<graphic_element> elements;
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struct BY_ID
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{
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bool operator()(const GEOM_GRAPHIC& lhs, const GEOM_GRAPHIC& rhs) const
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{
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return lhs.id < rhs.id;
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}
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};
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};
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std::vector<GEOM_GRAPHIC> board_graphics;
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std::map<std::string, std::map<int, GEOM_GRAPHIC>> comp_graphics;
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// A!VIA_X!VIA_Y!PAD_STACK_NAME!NET_NAME!TEST_POINT!
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struct FM_VIA
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{
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int x; ///<! VIA_X
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int y; ///<! VIA_Y
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std::string padstack; ///<! PAD_STACK_NAME
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std::string net; ///<! NET_NAME
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bool test_point; ///<! TEST_POINT
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bool mirror; ///<! VIA_MIRROR (VIA_MIRROR is an optional component)
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};
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std::vector<std::unique_ptr<FM_VIA>> vias;
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// A!CLASS!SUBCLASS!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!RECORD_TAG!GRAPHIC_DATA_1!
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// GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!
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// GRAPHIC_DATA_8!GRAPHIC_DATA_9!NET_NAME!
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struct TRACE
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{
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std::string lclass; ///<! CLASS
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std::string layer; ///<! SUBCLASS
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std::string netname; ///<! NET_NAME
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int id; ///<! RECORD_TAG[0]
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graphic_element segment; ///<! GRAPHIC_DATA (can be either LINE or ARC)
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struct BY_ID
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{
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bool operator()(const std::unique_ptr<TRACE>& lhs, const std::unique_ptr<TRACE>& rhs) const
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{
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return lhs->id < rhs->id;
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}
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};
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};
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std::set<std::unique_ptr<TRACE>, TRACE::BY_ID> traces;
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std::set<std::unique_ptr<TRACE>, TRACE::BY_ID> zones;
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std::set<std::unique_ptr<TRACE>, TRACE::BY_ID> polygons;
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// A!REFDES!COMP_CLASS!COMP_PART_NUMBER!COMP_HEIGHT!COMP_DEVICE_LABEL!COMP_INSERTION_CODE!SYM_TYPE!
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// SYM_NAME!SYM_MIRROR!SYM_ROTATE!SYM_X!SYM_Y!COMP_VALUE!COMP_TOL!COMP_VOLTAGE!
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struct COMPONENT
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{
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std::string refdes; ///<! REFDES
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COMPCLASS cclass; ///<! COMP_CLASS
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std::string pn; ///<! COMP_PART_NUMBER
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std::string height; ///<! COMP_HEIGHT
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std::string dev_label; ///<! COMP_DEVICE_LABEL
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std::string insert_code; ///<! COMP_INSERTION_CODE
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SYMTYPE type; ///<! SYM_TYPE
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std::string name; ///<! SYM_NAME
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bool mirror; ///<! SYM_MIRROR
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double rotate; ///<! SYM_ROTATE (degrees)
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int x; ///<! SYM_X
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int y; ///<! SYM_Y
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std::string value; ///<! COMP_VALUE
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std::string tol; ///<! COMP_TOL
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std::string voltage; ///<! COMP_VOLTAGE
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struct HASH
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{
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std::size_t operator()( const FABMASTER::COMPONENT& aCmp ) const
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{
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return std::hash<std::string>{}( aCmp.refdes );
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}
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};
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};
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std::map<std::string, std::vector<std::unique_ptr<COMPONENT>>> components;
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// A!SYM_NAME!SYM_MIRROR!PIN_NAME!PIN_NUMBER!PIN_X!PIN_Y!PAD_STACK_NAME!REFDES!PIN_ROTATION!TEST_POINT!
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struct PIN
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{
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std::string name; ///<! SYM_NAME
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bool mirror; ///<! SYM_MIRROR
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std::string pin_name; ///<! PIN_NAME
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std::string pin_number; ///<! PIN_NUMBER
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int pin_x; ///<! PIN_X - Absolute board units
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int pin_y; ///<! PIN_Y - Absolute board units
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std::string padstack; ///<! PAD_STACK
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std::string refdes; ///<! REFDES
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double rotation; ///<! PIN_ROTATION
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struct BY_NUM
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{
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bool operator()(const std::unique_ptr<PIN>& lhs,
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const std::unique_ptr<PIN>& rhs) const
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{
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return lhs->pin_number < rhs->pin_number;
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}
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};
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};
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std::map<std::string, std::set<std::unique_ptr<PIN>, PIN::BY_NUM>> pins;
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std::map<std::string, PCB_LAYER_ID> layer_map;
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section_type detectType( size_t aOffset );
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int execute_recordbuffer( int filetype );
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int getColFromName( size_t aRow, const std::string& aStr );
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SYMTYPE parseSymType( const std::string& aSymType );
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COMPCLASS parseCompClass( const std::string& aCompClass );
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/**
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* Processes data from text vectors into internal database
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* for further ordering
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* @param aRow vector offset being processed
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* @return Count of the number of rows processed
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*/
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double processScaleFactor( size_t aRow );
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size_t processPadStacks( size_t aRow );
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size_t processCustomPads( size_t aRow );
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size_t processGeometry( size_t aRow );
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size_t processVias( size_t aRow );
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size_t processTraces( size_t aRow );
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size_t processFootprints( size_t aRow );
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size_t processNets( size_t aRow );
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size_t processLayers( size_t aRow );
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size_t processSimpleLayers( size_t aRow );
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size_t processPadStackLayers( size_t aRow );
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size_t processSymbols( size_t aRow );
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size_t processPins( size_t aRow );
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/**
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* Specialty functions for processing graphical data rows into the internal
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|
* database
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* @param aData Loaded data vector
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* @param aScale Prior loaded scale factor
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* @return Pointer to newly allocated graphical item or nullptr on failure
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*/
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GRAPHIC_ITEM* processGraphic( const GRAPHIC_DATA& aData, double aScale );
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GRAPHIC_ARC* processArc( const GRAPHIC_DATA& aData, double aScale );
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GRAPHIC_LINE* processLine( const GRAPHIC_DATA& aData, double aScale );
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GRAPHIC_TEXT* processText( const GRAPHIC_DATA& aData, double aScale );
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GRAPHIC_RECTANGLE* processRectangle( const GRAPHIC_DATA& aData, double aScale );
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PCB_LAYER_ID getLayer( const std::string& aLayerName );
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bool assignLayers();
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/**
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* Sets zone priorities based on zone BB size. Larger bounding boxes get smaller priorities
|
|
* so smaller zones can knock out areas where they overlap.
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* @param aBoard
|
|
* @return True if successful
|
|
*/
|
|
bool orderZones( BOARD* aBoard );
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|
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/**
|
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* Loads sections of the database into the board
|
|
* @param aBoard
|
|
* @return True if successful
|
|
*/
|
|
bool loadZones( BOARD* aBoard );
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|
bool loadOutline( BOARD* aBoard, const std::unique_ptr<TRACE>& aLine);
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|
bool loadNets( BOARD* aBoard );
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bool loadLayers( BOARD* aBoard );
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|
bool loadGraphics( BOARD* aBoard );
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|
bool loadVias( BOARD* aBoard );
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bool loadEtch( BOARD* aBoard, const std::unique_ptr<TRACE>& aLine);
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|
bool loadZone( BOARD* aBoard, const std::unique_ptr<FABMASTER::TRACE>& aLine);
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bool loadPolygon( BOARD* aBoard, const std::unique_ptr<FABMASTER::TRACE>& aLine);
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bool loadFootprints( BOARD* aBoard );
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|
|
|
};
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#endif /* PCBNEW_IMPORTERS_IMPORT_FABMASTER_H_ */
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