342 lines
10 KiB
C++
342 lines
10 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2006 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com
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* Copyright (C) 2011 Wayne Stambaugh <stambaughw@verizon.net>
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* Copyright (C) 1992-2011 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @file editrack-part2.cpp
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*/
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#include "fctsys.h"
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#include "gr_basic.h"
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#include "class_drawpanel.h"
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#include "confirm.h"
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#include "wxPcbStruct.h"
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#include "pcbcommon.h"
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#include "class_board.h"
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#include "class_module.h"
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#include "class_track.h"
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#include "class_marker_pcb.h"
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#include "pcbnew.h"
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#include "drc_stuff.h"
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#include "protos.h"
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bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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{
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unsigned itmp;
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if( aTrack == NULL )
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{
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if( getActiveLayer() != ((PCB_SCREEN*)GetScreen())->m_Route_Layer_TOP )
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setActiveLayer( ((PCB_SCREEN*)GetScreen())->m_Route_Layer_TOP );
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else
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setActiveLayer(((PCB_SCREEN*)GetScreen())->m_Route_Layer_BOTTOM );
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UpdateStatusBar();
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return true;
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}
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/* Avoid more than one via on the current location: */
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if( GetBoard()->GetViaByPosition( g_CurrentTrackSegment->m_End,
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g_CurrentTrackSegment->GetLayer() ) )
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return false;
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for( TRACK* segm = g_FirstTrackSegment; segm; segm = segm->Next() )
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{
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if( segm->Type() == PCB_VIA_T && g_CurrentTrackSegment->m_End == segm->m_Start )
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return false;
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}
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/* Is the current segment Ok (no DRC error) ? */
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if( Drc_On )
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{
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if( BAD_DRC==m_drc->Drc( g_CurrentTrackSegment, GetBoard()->m_Track ) )
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/* DRC error, the change layer is not made */
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return false;
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// Handle 2 segments.
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if( g_TwoSegmentTrackBuild && g_CurrentTrackSegment->Back() )
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{
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if( BAD_DRC == m_drc->Drc( g_CurrentTrackSegment->Back(), GetBoard()->m_Track ) )
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return false;
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}
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}
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/* Save current state before placing a via.
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* If the via cannot be placed this current state will be reused
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*/
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itmp = g_CurrentTrackList.GetCount();
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Begin_Route( g_CurrentTrackSegment, DC );
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DrawPanel->m_mouseCaptureCallback( DrawPanel, DC, wxDefaultPosition, false );
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/* create the via */
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SEGVIA* via = new SEGVIA( GetBoard() );
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via->m_Flags = IS_NEW;
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via->m_Shape = GetBoard()->GetDesignSettings().m_CurrentViaType;
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via->m_Width = GetBoard()->GetCurrentViaSize();
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via->SetNet( GetBoard()->GetHighLightNetCode() );
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via->m_Start = via->m_End = g_CurrentTrackSegment->m_End;
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// Usual via is from copper to component.
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// layer pair is LAYER_N_BACK and LAYER_N_FRONT.
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via->SetLayerPair( LAYER_N_BACK, LAYER_N_FRONT );
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via->SetDrillValue( GetBoard()->GetCurrentViaDrill() );
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int first_layer = getActiveLayer();
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int last_layer;
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// prepare switch to new active layer:
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if( first_layer != GetScreen()->m_Route_Layer_TOP )
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last_layer = GetScreen()->m_Route_Layer_TOP;
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else
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last_layer = GetScreen()->m_Route_Layer_BOTTOM;
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/* Adjust the actual via layer pair */
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switch ( via->Shape() )
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{
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case VIA_BLIND_BURIED:
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via->SetLayerPair( first_layer, last_layer );
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break;
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case VIA_MICROVIA: // from external to the near neighbor inner layer
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{
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int last_inner_layer = GetBoard()->GetCopperLayerCount() - 2;
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if ( first_layer == LAYER_N_BACK )
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last_layer = LAYER_N_2;
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else if ( first_layer == LAYER_N_FRONT )
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last_layer = last_inner_layer;
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else if ( first_layer == LAYER_N_2 )
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last_layer = LAYER_N_BACK;
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else if ( first_layer == last_inner_layer )
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last_layer = LAYER_N_FRONT;
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// else error: will be removed later
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via->SetLayerPair( first_layer, last_layer );
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{
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NETINFO_ITEM* net = GetBoard()->FindNet( via->GetNet() );
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via->m_Width = net->GetMicroViaSize();
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}
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}
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break;
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default:
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break;
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}
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if( Drc_On && BAD_DRC == m_drc->Drc( via, GetBoard()->m_Track ) )
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{
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/* DRC fault: the Via cannot be placed here ... */
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delete via;
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DrawPanel->m_mouseCaptureCallback( DrawPanel, DC, wxDefaultPosition, false );
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// delete the track(s) added in Begin_Route()
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while( g_CurrentTrackList.GetCount() > itmp )
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{
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Delete_Segment( DC, g_CurrentTrackSegment );
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}
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SetCurItem( g_CurrentTrackSegment, false );
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// Refresh DRC diag, erased by previous calls
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if( m_drc->GetCurrentMarker() )
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m_drc->GetCurrentMarker()->DisplayInfo( this );
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return false;
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}
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setActiveLayer( last_layer );
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TRACK* lastNonVia = g_CurrentTrackSegment;
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/* A new via was created. It was Ok.
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*/
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g_CurrentTrackList.PushBack( via );
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/* The via is now in linked list and we need a new track segment
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* after the via, starting at via location.
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* it will become the new current segment (from via to the mouse cursor)
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*/
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TRACK* track = lastNonVia->Copy();
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/* the above creates a new segment from the last entered segment, with the
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* current width, flags, netcode, etc... values.
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* layer, start and end point are not correct,
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* and will be modified next
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*/
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// set the layer to the new value
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track->SetLayer( getActiveLayer() );
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/* the start point is the via position and the end point is the cursor
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* which also is on the via (will change when moving mouse)
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*/
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track->m_Start = track->m_End = via->m_Start;
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g_CurrentTrackList.PushBack( track );
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if( g_TwoSegmentTrackBuild )
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{
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// Create a second segment (we must have 2 track segments to adjust)
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g_CurrentTrackList.PushBack( g_CurrentTrackSegment->Copy() );
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}
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DrawPanel->m_mouseCaptureCallback( DrawPanel, DC, wxDefaultPosition, false );
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via->DisplayInfo( this );
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UpdateStatusBar();
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return true;
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}
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void PCB_EDIT_FRAME::DisplayNetStatus( wxDC* DC )
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{
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TRACK* pt_segm;
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int layerMask = (1 << getActiveLayer());
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wxPoint pos = GetScreen()->RefPos( true );
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pt_segm = GetBoard()->GetTrace( GetBoard()->m_Track, pos, layerMask );
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if( pt_segm == NULL )
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GetBoard()->DisplayInfo( this );
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else
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TestNetConnection( DC, pt_segm->GetNet() );
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}
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void PCB_EDIT_FRAME::Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC )
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{
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D_PAD* pt_pad = NULL;
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MODULE* Module = NULL;
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if( GetBoard()->IsElementVisible(RATSNEST_VISIBLE) )
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return;
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if( ( GetBoard()->m_Status_Pcb & LISTE_RATSNEST_ITEM_OK ) == 0 )
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Compile_Ratsnest( DC, true );
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if( item )
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{
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if( item->Type() == PCB_PAD_T )
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{
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pt_pad = (D_PAD*) item;
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Module = (MODULE*) pt_pad->GetParent();
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}
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if( pt_pad ) /* Displaying the ratsnest of the corresponding net. */
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{
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pt_pad->DisplayInfo( this );
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for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
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{
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RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
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if( net->GetNet() == pt_pad->GetNet() )
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{
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if( ( net->m_Status & CH_VISIBLE ) != 0 )
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continue;
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net->m_Status |= CH_VISIBLE;
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if( ( net->m_Status & CH_ACTIF ) == 0 )
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continue;
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net->Draw( DrawPanel, DC, GR_XOR, wxPoint( 0, 0 ) );
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}
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}
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}
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else
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{
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if( item->Type() == PCB_MODULE_TEXT_T )
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{
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if( item->GetParent() && ( item->GetParent()->Type() == PCB_MODULE_T ) )
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Module = (MODULE*) item->GetParent();
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}
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else if( item->Type() == PCB_MODULE_T )
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{
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Module = (MODULE*) item;
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}
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if( Module )
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{
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Module->DisplayInfo( this );
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pt_pad = Module->m_Pads;
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for( ; pt_pad != NULL; pt_pad = (D_PAD*) pt_pad->Next() )
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{
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for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
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{
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RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
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if( ( net->m_PadStart == pt_pad ) || ( net->m_PadEnd == pt_pad ) )
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{
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if( net->m_Status & CH_VISIBLE )
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continue;
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net->m_Status |= CH_VISIBLE;
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if( (net->m_Status & CH_ACTIF) == 0 )
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continue;
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net->Draw( DrawPanel, DC, GR_XOR, wxPoint( 0, 0 ) );
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}
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}
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}
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pt_pad = NULL;
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}
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}
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}
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/* Erase if no pad or module has been selected. */
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if( ( pt_pad == NULL ) && ( Module == NULL ) )
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{
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DrawGeneralRatsnest( DC );
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for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
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GetBoard()->m_FullRatsnest[ii].m_Status &= ~CH_VISIBLE;
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}
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}
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void PCB_EDIT_FRAME::HighlightUnconnectedPads( wxDC* DC )
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{
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for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
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{
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RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
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if( (net->m_Status & CH_ACTIF) == 0 )
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continue;
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net->m_PadStart->Draw( DrawPanel, DC, GR_OR | GR_HIGHLIGHT );
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net->m_PadEnd->Draw( DrawPanel, DC, GR_OR | GR_HIGHLIGHT );
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}
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}
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