208 lines
6.1 KiB
C++
208 lines
6.1 KiB
C++
/**
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* @brief NETINFO_ITEM class, to handle info on nets: netnames, net constraints
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*/
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <fctsys.h>
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#include <gr_basic.h>
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#include <class_drawpanel.h>
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#include <wxBasePcbFrame.h>
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#include <common.h>
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#include <kicad_string.h>
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#include <pcbnew.h>
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#include <colors_selection.h>
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#include <richio.h>
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#include <macros.h>
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#include <class_board.h>
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#include <class_module.h>
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#include <class_track.h>
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/*********************************************************/
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/* class NETINFO_ITEM: handle data relative to a given net */
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/*********************************************************/
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NETINFO_ITEM::NETINFO_ITEM( BOARD_ITEM* aParent, const wxString& aNetName, int aNetCode )
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{
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SetNet( aNetCode );
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if( aNetName.size() )
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SetNetname( aNetName );
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m_NbNodes = 0;
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m_NbLink = 0;
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m_NbNoconn = 0;
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m_Flag = 0;
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m_RatsnestStartIdx = 0; // Starting point of ratsnests of this net in a
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// general buffer of ratsnest
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m_RatsnestEndIdx = 0; // Ending point of ratsnests of this net
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m_NetClassName = NETCLASS::Default;
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m_NetClass = 0;
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}
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NETINFO_ITEM::~NETINFO_ITEM()
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{
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// m_NetClass is not owned by me.
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}
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/**
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* Function SetNetname
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* @param aNetname : the new netname
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*/
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void NETINFO_ITEM::SetNetname( const wxString& aNetname )
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{
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m_Netname = aNetname;
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m_ShortNetname = m_Netname.AfterLast( '/' );
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}
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/**
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* Function Draw (TODO)
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*/
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void NETINFO_ITEM::Draw( EDA_DRAW_PANEL* panel,
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wxDC* DC,
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GR_DRAWMODE aDrawMode,
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const wxPoint& aOffset )
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{
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}
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/**
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* Function DisplayInfo
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* has knowledge about the frame and how and where to put status information
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* about this object into the frame's message panel.
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* Is virtual from EDA_ITEM.
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* @param frame A EDA_DRAW_FRAME in which to print status information.
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*/
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void NETINFO_ITEM::DisplayInfo( EDA_DRAW_FRAME* frame )
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{
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int count;
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EDA_ITEM* Struct;
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wxString txt;
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MODULE* module;
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D_PAD* pad;
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double lengthnet = 0; // This is the lenght of tracks on pcb
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double lengthdie = 0; // this is the lenght of internal ICs connections
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frame->ClearMsgPanel();
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frame->AppendMsgPanel( _( "Net Name" ), GetNetname(), RED );
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txt.Printf( wxT( "%d" ), GetNet() );
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frame->AppendMsgPanel( _( "Net Code" ), txt, RED );
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count = 0;
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module = ( (PCB_BASE_FRAME*) frame )->GetBoard()->m_Modules;
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for( ; module != 0; module = module->Next() )
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{
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for( pad = module->m_Pads; pad != 0; pad = pad->Next() )
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{
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if( pad->GetNet() == GetNet() )
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{
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count++;
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lengthdie += pad->GetDieLength();
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}
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}
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}
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txt.Printf( wxT( "%d" ), count );
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frame->AppendMsgPanel( _( "Pads" ), txt, DARKGREEN );
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count = 0;
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Struct = ( (PCB_BASE_FRAME*) frame )->GetBoard()->m_Track;
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for( ; Struct != NULL; Struct = Struct->Next() )
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{
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if( Struct->Type() == PCB_VIA_T )
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{
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if( ( (SEGVIA*) Struct )->GetNet() == GetNet() )
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count++;
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}
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if( Struct->Type() == PCB_TRACE_T )
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{
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if( ( (TRACK*) Struct )->GetNet() == GetNet() )
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lengthnet += ( (TRACK*) Struct )->GetLength();
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}
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}
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txt.Printf( wxT( "%d" ), count );
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frame->AppendMsgPanel( _( "Vias" ), txt, BLUE );
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// Displays the full net lenght (tracks on pcb + internal ICs connections ):
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txt = frame->CoordinateToString( lengthnet + lengthdie );
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frame->AppendMsgPanel( _( "Net Length:" ), txt, RED );
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// Displays the net lenght of tracks only:
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txt = frame->CoordinateToString( lengthnet );
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frame->AppendMsgPanel( _( "On Board" ), txt, RED );
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// Displays the net lenght of internal ICs connections (wires inside ICs):
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txt = frame->CoordinateToString( lengthdie );
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frame->AppendMsgPanel( _( "On Die" ), txt, RED );
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}
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/***********************/
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/* class RATSNEST_ITEM */
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/***********************/
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RATSNEST_ITEM::RATSNEST_ITEM()
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{
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m_NetCode = 0; // netcode ( = 1.. n , 0 is the value used for not
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// connected items)
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m_Status = 0; // state
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m_PadStart = NULL; // pointer to the starting pad
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m_PadEnd = NULL; // pointer to ending pad
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m_Lenght = 0; // length of the line (temporary used in some
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// calculations)
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}
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/**
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* Function Draw
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* Draws a line (a ratsnest) from the starting pad to the ending pad
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*/
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void RATSNEST_ITEM::Draw( EDA_DRAW_PANEL* panel,
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wxDC* DC,
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GR_DRAWMODE aDrawMode,
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const wxPoint& aOffset )
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{
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GRSetDrawMode( DC, aDrawMode );
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EDA_COLOR_T color = g_ColorsSettings.GetItemColor(RATSNEST_VISIBLE);
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GRLine( panel->GetClipBox(), DC,
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m_PadStart->GetPosition() - aOffset,
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m_PadEnd->GetPosition() - aOffset, 0, color );
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}
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