kicad/demos/sonde xilinx
jean-pierre charras 0cb6cd8c02 Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy.
Known bug in intermediate netlist generation: multi parts per package have their common pins listed more than once in nets section. Will be fixed.
2011-02-10 09:27:36 +01:00
..
sonde xilinx-cache.lib Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy. 2011-02-10 09:27:36 +01:00
sonde xilinx.brd fixed bug 583939 2010-05-23 19:39:47 +02:00
sonde xilinx.cmp add files not currently available in source (e.g. docs, modules, etc.) 2007-06-05 12:10:51 +00:00
sonde xilinx.drl add files not currently available in source (e.g. docs, modules, etc.) 2007-06-05 12:10:51 +00:00
sonde xilinx.net add files not currently available in source (e.g. docs, modules, etc.) 2007-06-05 12:10:51 +00:00
sonde xilinx.pro fixed bug 585140 and minor cleaning 2010-05-27 12:23:29 +02:00
sonde xilinx.sch Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy. 2011-02-10 09:27:36 +01:00