351 lines
13 KiB
C++
351 lines
13 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2014 CERN
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* @author Maciej Suminski <maciej.suminski@cern.ch>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "pcb_draw_panel_gal.h"
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#include <view/view.h>
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#include <view/wx_view_controls.h>
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#include <pcb_painter.h>
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#include <worksheet_viewitem.h>
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#include <ratsnest_viewitem.h>
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#include <class_colors_design_settings.h>
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#include <class_board.h>
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#include <class_module.h>
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#include <class_track.h>
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#include <pcbcommon.h>
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#include <boost/bind.hpp>
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const LAYER_NUM GAL_LAYER_ORDER[] =
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{
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ITEM_GAL_LAYER( GP_OVERLAY ),
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ITEM_GAL_LAYER( DRC_VISIBLE ),
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NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
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Dwgs_User, Cmts_User, Eco1_User, Eco2_User, Edge_Cuts,
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ITEM_GAL_LAYER( MOD_TEXT_FR_VISIBLE ),
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ITEM_GAL_LAYER( MOD_REFERENCES_VISIBLE), ITEM_GAL_LAYER( MOD_VALUES_VISIBLE ),
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ITEM_GAL_LAYER( RATSNEST_VISIBLE ), ITEM_GAL_LAYER( ANCHOR_VISIBLE ),
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ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),
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ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ), ITEM_GAL_LAYER( VIA_BBLIND_VISIBLE ),
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ITEM_GAL_LAYER( VIA_MICROVIA_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
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NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ), F_Mask,
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NETNAMES_GAL_LAYER( F_Cu ), F_Cu,
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F_SilkS, F_Paste, F_Adhes,
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#if 0 // was:
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NETNAMES_GAL_LAYER( LAYER_15_NETNAMES_VISIBLE ), LAYER_N_15,
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NETNAMES_GAL_LAYER( LAYER_14_NETNAMES_VISIBLE ), LAYER_N_14,
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NETNAMES_GAL_LAYER( LAYER_13_NETNAMES_VISIBLE ), LAYER_N_13,
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NETNAMES_GAL_LAYER( LAYER_12_NETNAMES_VISIBLE ), LAYER_N_12,
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NETNAMES_GAL_LAYER( LAYER_11_NETNAMES_VISIBLE ), LAYER_N_11,
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NETNAMES_GAL_LAYER( LAYER_10_NETNAMES_VISIBLE ), LAYER_N_10,
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NETNAMES_GAL_LAYER( LAYER_9_NETNAMES_VISIBLE ), LAYER_N_9,
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NETNAMES_GAL_LAYER( LAYER_8_NETNAMES_VISIBLE ), LAYER_N_8,
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NETNAMES_GAL_LAYER( LAYER_7_NETNAMES_VISIBLE ), LAYER_N_7,
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NETNAMES_GAL_LAYER( LAYER_6_NETNAMES_VISIBLE ), LAYER_N_6,
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NETNAMES_GAL_LAYER( LAYER_5_NETNAMES_VISIBLE ), LAYER_N_5,
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NETNAMES_GAL_LAYER( LAYER_4_NETNAMES_VISIBLE ), LAYER_N_4,
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NETNAMES_GAL_LAYER( LAYER_3_NETNAMES_VISIBLE ), LAYER_N_3,
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NETNAMES_GAL_LAYER( LAYER_2_NETNAMES_VISIBLE ), LAYER_N_2,
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#else
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NETNAMES_GAL_LAYER( In1_Cu ), In1_Cu,
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NETNAMES_GAL_LAYER( In2_Cu ), In2_Cu,
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NETNAMES_GAL_LAYER( In3_Cu ), In3_Cu,
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NETNAMES_GAL_LAYER( In4_Cu ), In4_Cu,
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NETNAMES_GAL_LAYER( In5_Cu ), In5_Cu,
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NETNAMES_GAL_LAYER( In6_Cu ), In6_Cu,
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NETNAMES_GAL_LAYER( In7_Cu ), In7_Cu,
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NETNAMES_GAL_LAYER( In8_Cu ), In8_Cu,
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NETNAMES_GAL_LAYER( In9_Cu ), In9_Cu,
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NETNAMES_GAL_LAYER( In10_Cu ), In10_Cu,
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NETNAMES_GAL_LAYER( In11_Cu ), In11_Cu,
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NETNAMES_GAL_LAYER( In12_Cu ), In12_Cu,
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NETNAMES_GAL_LAYER( In13_Cu ), In13_Cu,
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NETNAMES_GAL_LAYER( In14_Cu ), In14_Cu,
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NETNAMES_GAL_LAYER( In15_Cu ), In15_Cu,
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NETNAMES_GAL_LAYER( In16_Cu ), In16_Cu,
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NETNAMES_GAL_LAYER( In17_Cu ), In17_Cu,
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NETNAMES_GAL_LAYER( In18_Cu ), In18_Cu,
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NETNAMES_GAL_LAYER( In19_Cu ), In19_Cu,
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NETNAMES_GAL_LAYER( In20_Cu ), In20_Cu,
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NETNAMES_GAL_LAYER( In21_Cu ), In21_Cu,
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NETNAMES_GAL_LAYER( In22_Cu ), In22_Cu,
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NETNAMES_GAL_LAYER( In23_Cu ), In23_Cu,
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NETNAMES_GAL_LAYER( In24_Cu ), In24_Cu,
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NETNAMES_GAL_LAYER( In25_Cu ), In25_Cu,
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NETNAMES_GAL_LAYER( In26_Cu ), In26_Cu,
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NETNAMES_GAL_LAYER( In27_Cu ), In27_Cu,
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NETNAMES_GAL_LAYER( In28_Cu ), In28_Cu,
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NETNAMES_GAL_LAYER( In29_Cu ), In29_Cu,
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NETNAMES_GAL_LAYER( In30_Cu ), In30_Cu,
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#endif
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NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ), B_Mask,
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NETNAMES_GAL_LAYER( B_Cu ), B_Cu,
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B_Adhes, B_Paste, B_SilkS,
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ITEM_GAL_LAYER( MOD_TEXT_BK_VISIBLE ),
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ITEM_GAL_LAYER( WORKSHEET )
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};
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PCB_DRAW_PANEL_GAL::PCB_DRAW_PANEL_GAL( wxWindow* aParentWindow, wxWindowID aWindowId,
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const wxPoint& aPosition, const wxSize& aSize,
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GalType aGalType ) :
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EDA_DRAW_PANEL_GAL( aParentWindow, aWindowId, aPosition, aSize, aGalType )
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{
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m_worksheet = NULL;
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m_ratsnest = NULL;
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// Set rendering order and properties of layers
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for( LAYER_NUM i = 0; (unsigned) i < sizeof(GAL_LAYER_ORDER) / sizeof(LAYER_NUM); ++i )
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{
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LAYER_NUM layer = GAL_LAYER_ORDER[i];
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wxASSERT( layer < KIGFX::VIEW::VIEW_MAX_LAYERS );
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m_view->SetLayerOrder( layer, i );
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if( IsCopperLayer( layer ) )
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{
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// Copper layers are required for netname layers
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m_view->SetRequired( GetNetnameLayer( layer ), layer );
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m_view->SetLayerTarget( layer, KIGFX::TARGET_CACHED );
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}
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else if( IsNetnameLayer( layer ) )
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{
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// Netnames are drawn only when scale is sufficient (level of details)
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// so there is no point in caching them
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m_view->SetLayerTarget( layer, KIGFX::TARGET_NONCACHED );
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}
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}
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m_view->SetLayerTarget( ITEM_GAL_LAYER( ANCHOR_VISIBLE ), KIGFX::TARGET_NONCACHED );
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// Some more required layers settings
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m_view->SetRequired( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ) );
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m_view->SetRequired( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
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m_view->SetRequired( NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
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m_view->SetRequired( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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m_view->SetRequired( F_Adhes, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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m_view->SetRequired( F_Paste, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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m_view->SetRequired( F_Mask, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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m_view->SetRequired( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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m_view->SetRequired( B_Adhes, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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m_view->SetRequired( B_Paste, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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m_view->SetRequired( B_Mask, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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m_view->SetRequired( ITEM_GAL_LAYER( PAD_FR_VISIBLE ), ITEM_GAL_LAYER( MOD_FR_VISIBLE ) );
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m_view->SetRequired( ITEM_GAL_LAYER( PAD_BK_VISIBLE ), ITEM_GAL_LAYER( MOD_BK_VISIBLE ) );
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m_view->SetLayerTarget( ITEM_GAL_LAYER( GP_OVERLAY ), KIGFX::TARGET_OVERLAY );
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m_view->SetLayerTarget( ITEM_GAL_LAYER( RATSNEST_VISIBLE ), KIGFX::TARGET_OVERLAY );
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// Load display options (such as filled/outline display of items)
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static_cast<KIGFX::PCB_RENDER_SETTINGS*>( m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( DisplayOpt );
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}
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PCB_DRAW_PANEL_GAL::~PCB_DRAW_PANEL_GAL()
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{
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delete m_worksheet;
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delete m_ratsnest;
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}
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void PCB_DRAW_PANEL_GAL::DisplayBoard( const BOARD* aBoard )
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{
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m_view->Clear();
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// Load zones
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for( int i = 0; i < aBoard->GetAreaCount(); ++i )
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m_view->Add( (KIGFX::VIEW_ITEM*) ( aBoard->GetArea( i ) ) );
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// Load drawings
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for( BOARD_ITEM* drawing = aBoard->m_Drawings; drawing; drawing = drawing->Next() )
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m_view->Add( drawing );
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// Load tracks
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for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
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m_view->Add( track );
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// Load modules and its additional elements
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for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
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{
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module->RunOnChildren( boost::bind( &KIGFX::VIEW::Add, m_view, _1 ) );
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m_view->Add( module );
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}
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// Segzones (equivalent of ZONE_CONTAINER for legacy boards)
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for( SEGZONE* zone = aBoard->m_Zone; zone; zone = zone->Next() )
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m_view->Add( zone );
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// Ratsnest
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if( m_ratsnest )
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{
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m_view->Remove( m_ratsnest );
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delete m_ratsnest;
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}
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m_ratsnest = new KIGFX::RATSNEST_VIEWITEM( aBoard->GetRatsnest() );
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m_view->Add( m_ratsnest );
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UseColorScheme( aBoard->GetColorsSettings() );
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m_view->RecacheAllItems( true );
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}
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void PCB_DRAW_PANEL_GAL::SetWorksheet( KIGFX::WORKSHEET_VIEWITEM* aWorksheet )
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{
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if( m_worksheet )
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{
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m_view->Remove( m_worksheet );
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delete m_worksheet;
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}
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m_worksheet = aWorksheet;
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m_view->Add( m_worksheet );
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}
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void PCB_DRAW_PANEL_GAL::UseColorScheme( const COLORS_DESIGN_SETTINGS* aSettings )
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{
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KIGFX::PCB_RENDER_SETTINGS* rs;
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rs = static_cast<KIGFX::PCB_RENDER_SETTINGS*>( m_view->GetPainter()->GetSettings() );
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rs->ImportLegacyColors( aSettings );
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}
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void PCB_DRAW_PANEL_GAL::SetHighContrastLayer( LAYER_ID aLayer )
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{
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// Set display settings for high contrast mode
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KIGFX::RENDER_SETTINGS* rSettings = m_view->GetPainter()->GetSettings();
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SetTopLayer( aLayer );
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rSettings->ClearActiveLayers();
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rSettings->SetActiveLayer( aLayer );
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if( IsCopperLayer( aLayer ) )
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{
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// Bring some other layers to the front in case of copper layers and make them colored
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// fixme do not like the idea of storing the list of layers here,
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// should be done in some other way I guess..
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LAYER_NUM layers[] = {
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GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ),
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ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
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ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
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ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE )
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};
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for( unsigned int i = 0; i < sizeof( layers ) / sizeof( LAYER_NUM ); ++i )
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rSettings->SetActiveLayer( layers[i] );
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// Pads should be shown too
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if( aLayer == B_Cu )
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{
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rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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rSettings->SetActiveLayer( ITEM_GAL_LAYER( MOD_BK_VISIBLE ) );
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rSettings->SetActiveLayer( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
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}
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else if( aLayer == F_Cu )
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{
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rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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rSettings->SetActiveLayer( ITEM_GAL_LAYER( MOD_FR_VISIBLE ) );
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rSettings->SetActiveLayer( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
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}
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}
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m_view->UpdateAllLayersColor();
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}
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void PCB_DRAW_PANEL_GAL::SetTopLayer( LAYER_ID aLayer )
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{
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m_view->ClearTopLayers();
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m_view->SetTopLayer( aLayer );
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if( IsCopperLayer( aLayer ) )
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{
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// Bring some other layers to the front in case of copper layers and make them colored
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// fixme do not like the idea of storing the list of layers here,
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// should be done in some other way I guess..
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LAYER_NUM layers[] = {
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GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ),
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ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
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ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
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ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE ), Dwgs_User,
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ITEM_GAL_LAYER( DRC_VISIBLE )
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};
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for( unsigned int i = 0; i < sizeof( layers ) / sizeof( LAYER_NUM ); ++i )
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{
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m_view->SetTopLayer( layers[i] );
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}
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// Pads should be shown too
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if( aLayer == B_Cu )
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{
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m_view->SetTopLayer( ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
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m_view->SetTopLayer( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
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}
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else if( aLayer == F_Cu )
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{
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m_view->SetTopLayer( ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
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m_view->SetTopLayer( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
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}
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}
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m_view->UpdateAllLayersOrder();
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}
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void PCB_DRAW_PANEL_GAL::SyncLayersVisibility( const BOARD* aBoard )
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{
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// Load layer & elements visibility settings
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for( LAYER_NUM i = 0; i < LAYER_ID_COUNT; ++i )
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{
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m_view->SetLayerVisible( i, aBoard->IsLayerVisible( LAYER_ID( i ) ) );
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// Synchronize netname layers as well
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if( IsCopperLayer( i ) )
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m_view->SetLayerVisible( GetNetnameLayer( i ), aBoard->IsLayerVisible( LAYER_ID( i ) ) );
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}
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for( LAYER_NUM i = 0; i < END_PCB_VISIBLE_LIST; ++i )
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{
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m_view->SetLayerVisible( ITEM_GAL_LAYER( i ), aBoard->IsElementVisible( i ) );
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}
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// Enable some layers that are GAL specific
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m_view->SetLayerVisible( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), true );
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m_view->SetLayerVisible( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), true );
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m_view->SetLayerVisible( ITEM_GAL_LAYER( WORKSHEET ), true );
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m_view->SetLayerVisible( ITEM_GAL_LAYER( GP_OVERLAY ), true );
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}
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