Seth Hillbrand 2451cbddec Consolidate Maximum clearance calculation ... We were calculating the same thing in three locations and we missed adding the clearance from the footprints in, resulting in bad fills and missed drc errors (see QA addition) (cherry picked from commit 96a34e5b57)		2023-07-26 13:16:32 -07:00
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common	Coverity fixes and code cleaning.	2023-03-10 11:21:19 -05:00
eeschema	Connectivity: Correct alias-based bus resolution	2023-06-02 14:25:26 -07:00
gerbview	Move KIPLATFORM::APP::Init in qa_gerbview	2022-08-08 22:31:41 -04:00
libs	Add EDA_ANGLE::NormalizeNegative() and qa tests	2023-01-30 19:56:22 +00:00
pcbnew	Consolidate Maximum clearance calculation	2023-07-26 13:16:32 -07:00
CMakeLists.txt	Refactor step export to use our normal board processing routines	2022-11-12 21:27:10 -05:00