288 lines
10 KiB
C++
288 lines
10 KiB
C++
// Copyright 2017 The Crashpad Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "snapshot/linux/cpu_context_linux.h"
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#include <stddef.h>
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#include <string.h>
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#include <limits>
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#include "base/logging.h"
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namespace crashpad {
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namespace internal {
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#if defined(ARCH_CPU_X86_FAMILY)
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#define SET_GPRS32() \
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do { \
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context->eax = thread_context.eax; \
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context->ebx = thread_context.ebx; \
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context->ecx = thread_context.ecx; \
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context->edx = thread_context.edx; \
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context->edi = thread_context.edi; \
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context->esi = thread_context.esi; \
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context->ebp = thread_context.ebp; \
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context->esp = thread_context.esp; \
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context->eip = thread_context.eip; \
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context->eflags = thread_context.eflags; \
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context->cs = thread_context.xcs; \
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context->ds = thread_context.xds; \
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context->es = thread_context.xes; \
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context->fs = thread_context.xfs; \
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context->gs = thread_context.xgs; \
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context->ss = thread_context.xss; \
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} while (false)
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void InitializeCPUContextX86(const ThreadContext::t32_t& thread_context,
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const FloatContext::f32_t& float_context,
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CPUContextX86* context) {
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SET_GPRS32();
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static_assert(sizeof(context->fxsave) == sizeof(float_context.fxsave),
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"fxsave size mismatch");
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memcpy(&context->fxsave, &float_context.fxsave, sizeof(context->fxsave));
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// TODO(jperaza): debug registers
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context->dr0 = 0;
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context->dr1 = 0;
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context->dr2 = 0;
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context->dr3 = 0;
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context->dr4 = 0;
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context->dr5 = 0;
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context->dr6 = 0;
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context->dr7 = 0;
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}
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void InitializeCPUContextX86(const SignalThreadContext32& thread_context,
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const SignalFloatContext32& float_context,
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CPUContextX86* context) {
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InitializeCPUContextX86_NoFloatingPoint(thread_context, context);
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CPUContextX86::FsaveToFxsave(float_context.fsave, &context->fxsave);
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}
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void InitializeCPUContextX86_NoFloatingPoint(
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const SignalThreadContext32& thread_context,
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CPUContextX86* context) {
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SET_GPRS32();
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memset(&context->fxsave, 0, sizeof(context->fxsave));
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context->dr0 = 0;
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context->dr1 = 0;
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context->dr2 = 0;
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context->dr3 = 0;
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context->dr4 = 0;
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context->dr5 = 0;
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context->dr6 = 0;
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context->dr7 = 0;
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}
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#define SET_GPRS64() \
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do { \
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context->rax = thread_context.rax; \
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context->rbx = thread_context.rbx; \
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context->rcx = thread_context.rcx; \
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context->rdx = thread_context.rdx; \
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context->rdi = thread_context.rdi; \
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context->rsi = thread_context.rsi; \
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context->rbp = thread_context.rbp; \
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context->rsp = thread_context.rsp; \
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context->r8 = thread_context.r8; \
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context->r9 = thread_context.r9; \
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context->r10 = thread_context.r10; \
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context->r11 = thread_context.r11; \
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context->r12 = thread_context.r12; \
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context->r13 = thread_context.r13; \
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context->r14 = thread_context.r14; \
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context->r15 = thread_context.r15; \
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context->rip = thread_context.rip; \
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context->rflags = thread_context.eflags; \
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context->cs = thread_context.cs; \
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context->fs = thread_context.fs; \
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context->gs = thread_context.gs; \
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} while (false)
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void InitializeCPUContextX86_64(const ThreadContext::t64_t& thread_context,
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const FloatContext::f64_t& float_context,
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CPUContextX86_64* context) {
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SET_GPRS64();
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static_assert(sizeof(context->fxsave) == sizeof(float_context.fxsave),
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"fxsave size mismatch");
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memcpy(&context->fxsave, &float_context.fxsave, sizeof(context->fxsave));
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// TODO(jperaza): debug registers.
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context->dr0 = 0;
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context->dr1 = 0;
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context->dr2 = 0;
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context->dr3 = 0;
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context->dr4 = 0;
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context->dr5 = 0;
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context->dr6 = 0;
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context->dr7 = 0;
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}
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void InitializeCPUContextX86_64(const SignalThreadContext64& thread_context,
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const SignalFloatContext64& float_context,
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CPUContextX86_64* context) {
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SET_GPRS64();
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static_assert(
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std::is_same<SignalFloatContext64, CPUContextX86_64::Fxsave>::value,
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"signal float context has unexpected type");
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memcpy(&context->fxsave, &float_context, sizeof(context->fxsave));
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context->dr0 = 0;
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context->dr1 = 0;
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context->dr2 = 0;
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context->dr3 = 0;
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context->dr4 = 0;
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context->dr5 = 0;
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context->dr6 = 0;
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context->dr7 = 0;
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}
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void InitializeCPUContextX86_64_NoFloatingPoint(
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const SignalThreadContext64& thread_context,
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CPUContextX86_64* context) {
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SET_GPRS64();
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memset(&context->fxsave, 0, sizeof(context->fxsave));
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context->dr0 = 0;
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context->dr1 = 0;
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context->dr2 = 0;
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context->dr3 = 0;
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context->dr4 = 0;
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context->dr5 = 0;
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context->dr6 = 0;
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context->dr7 = 0;
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}
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#elif defined(ARCH_CPU_ARM_FAMILY)
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void InitializeCPUContextARM(const ThreadContext::t32_t& thread_context,
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const FloatContext::f32_t& float_context,
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CPUContextARM* context) {
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static_assert(sizeof(context->regs) == sizeof(thread_context.regs),
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"registers size mismatch");
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memcpy(&context->regs, &thread_context.regs, sizeof(context->regs));
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context->fp = thread_context.fp;
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context->ip = thread_context.ip;
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context->sp = thread_context.sp;
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context->lr = thread_context.lr;
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context->pc = thread_context.pc;
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context->cpsr = thread_context.cpsr;
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static_assert(sizeof(context->vfp_regs) == sizeof(float_context.vfp),
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"vfp size mismatch");
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context->have_vfp_regs = float_context.have_vfp;
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if (float_context.have_vfp) {
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memcpy(&context->vfp_regs, &float_context.vfp, sizeof(context->vfp_regs));
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}
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static_assert(sizeof(context->fpa_regs) == sizeof(float_context.fpregs),
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"fpregs size mismatch");
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context->have_fpa_regs = float_context.have_fpregs;
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if (float_context.have_fpregs) {
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memcpy(
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&context->fpa_regs, &float_context.fpregs, sizeof(context->fpa_regs));
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}
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}
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void InitializeCPUContextARM_NoFloatingPoint(
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const SignalThreadContext32& thread_context,
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CPUContextARM* context) {
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static_assert(sizeof(context->regs) == sizeof(thread_context.regs),
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"registers size mismatch");
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memcpy(&context->regs, &thread_context.regs, sizeof(context->regs));
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context->fp = thread_context.fp;
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context->ip = thread_context.ip;
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context->sp = thread_context.sp;
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context->lr = thread_context.lr;
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context->pc = thread_context.pc;
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context->cpsr = thread_context.cpsr;
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memset(&context->fpa_regs, 0, sizeof(context->fpa_regs));
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memset(&context->vfp_regs, 0, sizeof(context->vfp_regs));
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context->have_fpa_regs = false;
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context->have_vfp_regs = false;
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}
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void InitializeCPUContextARM64(const ThreadContext::t64_t& thread_context,
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const FloatContext::f64_t& float_context,
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CPUContextARM64* context) {
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InitializeCPUContextARM64_NoFloatingPoint(thread_context, context);
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static_assert(sizeof(context->fpsimd) == sizeof(float_context.vregs),
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"fpsimd context size mismatch");
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memcpy(context->fpsimd, float_context.vregs, sizeof(context->fpsimd));
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context->fpsr = float_context.fpsr;
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context->fpcr = float_context.fpcr;
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}
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void InitializeCPUContextARM64_NoFloatingPoint(
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const ThreadContext::t64_t& thread_context,
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CPUContextARM64* context) {
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static_assert(sizeof(context->regs) == sizeof(thread_context.regs),
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"gpr context size mismtach");
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memcpy(context->regs, thread_context.regs, sizeof(context->regs));
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context->sp = thread_context.sp;
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context->pc = thread_context.pc;
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// Linux seems to only be putting the SPSR register in its "pstate" field.
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// https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/ptrace.h
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if (thread_context.pstate >
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std::numeric_limits<decltype(context->spsr)>::max()) {
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LOG(WARNING) << "pstate truncation: we only expect the SPSR bits to be set "
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"in the pstate";
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}
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context->spsr = static_cast<decltype(context->spsr)>(thread_context.pstate);
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memset(&context->fpsimd, 0, sizeof(context->fpsimd));
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context->fpsr = 0;
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context->fpcr = 0;
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}
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void InitializeCPUContextARM64_OnlyFPSIMD(
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const SignalFPSIMDContext& float_context,
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CPUContextARM64* context) {
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static_assert(sizeof(context->fpsimd) == sizeof(float_context.vregs),
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"fpsimd context size mismatch");
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memcpy(context->fpsimd, float_context.vregs, sizeof(context->fpsimd));
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context->fpsr = float_context.fpsr;
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context->fpcr = float_context.fpcr;
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}
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#elif defined(ARCH_CPU_RISCV64)
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void InitializeCPUContextRISCV64(const ThreadContext::t64_t& thread_context,
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const FloatContext::f64_t& float_context,
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CPUContextRISCV64* context) {
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context->pc = thread_context.pc;
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static_assert(sizeof(context->regs) == sizeof(thread_context.regs));
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memcpy(context->regs, thread_context.regs, sizeof(context->regs));
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static_assert(sizeof(context->fpregs) == sizeof(float_context.fpregs));
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memcpy(context->fpregs, float_context.fpregs, sizeof(context->fpregs));
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context->fcsr = float_context.fcsr;
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}
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#endif // ARCH_CPU_X86_FAMILY
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} // namespace internal
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} // namespace crashpad
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