Jeff Young fdf71ba005 Fix linker error (doubly defined symbol).		2022-09-10 10:26:10 +01:00
..
data	Add ERC QA tests	2022-09-09 17:21:57 -07:00
ibis	Rename signalIntegrity to ibis	2022-06-10 13:35:48 -07:00
mocks	Add ERC QA tests	2022-09-09 17:21:57 -07:00
pcbnew_utils	Don't link gdiplus everywhere anymore	2022-08-23 23:51:35 -04:00
qa_utils	Better feedback for netclass assignment patterns.	2022-09-03 21:33:56 +01:00
resources/linux	Fix source comment / documentation typos	2021-06-09 19:32:58 +00:00
schematic_utils	Fix linker error (doubly defined symbol).	2022-09-10 10:26:10 +01:00
testcases	qa: move pcbnew data to appropriate directory	2022-03-30 11:13:23 +00:00
tools	Silence msvc warning about printf	2022-08-26 19:26:51 -04:00
unittests	Sim QA: Display the original netlist even if circuit fails to parse	2022-09-10 02:45:48 +02:00
CMakeLists.txt	Add ERC QA tests	2022-09-09 17:21:57 -07:00
test.py	QA test code: fix some issues:	2022-01-06 09:37:14 +01:00