507 lines
16 KiB
C++
507 lines
16 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2015 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 2012 Wayne Stambaugh <stambaughw@verizon.net>
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* Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @file editrack-part2.cpp
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*/
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#include <fctsys.h>
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#include <gr_basic.h>
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#include <class_drawpanel.h>
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#include <confirm.h>
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#include <pcb_edit_frame.h>
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#include <class_board.h>
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#include <class_module.h>
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#include <class_track.h>
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#include <class_marker_pcb.h>
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#include <pcbnew.h>
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#include <drc.h>
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#include <connectivity_data.h>
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bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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{
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unsigned itmp;
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if( aTrack == NULL )
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{
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if( GetActiveLayer() != GetScreen()->m_Route_Layer_TOP )
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SetActiveLayer( GetScreen()->m_Route_Layer_TOP );
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else
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SetActiveLayer( GetScreen()->m_Route_Layer_BOTTOM );
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UpdateStatusBar();
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return true;
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}
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// Avoid more than one via on the current location:
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if( GetBoard()->GetViaByPosition( g_CurrentTrackSegment->GetEnd(),
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g_CurrentTrackSegment->GetLayer() ) )
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return false;
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for( TRACK* segm = g_FirstTrackSegment; segm; segm = segm->Next() )
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{
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if( segm->Type() == PCB_VIA_T && g_CurrentTrackSegment->GetEnd() == segm->GetStart() )
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return false;
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}
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// Is the current segment Ok (no DRC error) ?
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if( Settings().m_legacyDrcOn )
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{
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if( BAD_DRC==m_drc->Drc( g_CurrentTrackSegment, GetBoard()->m_Track ) )
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// DRC error, the change layer is not made
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return false;
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// Handle 2 segments.
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if( Settings().m_legacyUseTwoSegmentTracks && g_CurrentTrackSegment->Back() )
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{
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if( BAD_DRC == m_drc->Drc( g_CurrentTrackSegment->Back(), GetBoard()->m_Track ) )
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return false;
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}
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}
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/* Save current state before placing a via.
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* If the via cannot be placed this current state will be reused
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*/
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itmp = g_CurrentTrackList.GetCount();
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Begin_Route( g_CurrentTrackSegment, DC );
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m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
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// create the via
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VIA* via = new VIA( GetBoard() );
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via->SetFlags( IS_NEW );
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via->SetViaType( GetDesignSettings().m_CurrentViaType );
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via->SetNetCode( GetBoard()->GetHighLightNetCode() );
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via->SetPosition( g_CurrentTrackSegment->GetEnd() );
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// for microvias, the size and hole will be changed later.
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via->SetWidth( GetDesignSettings().GetCurrentViaSize());
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via->SetDrill( GetDesignSettings().GetCurrentViaDrill() );
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// Usual via is from copper to component.
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// layer pair is B_Cu and F_Cu.
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via->SetLayerPair( B_Cu, F_Cu );
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PCB_LAYER_ID first_layer = GetActiveLayer();
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PCB_LAYER_ID last_layer;
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// prepare switch to new active layer:
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if( first_layer != GetScreen()->m_Route_Layer_TOP )
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last_layer = GetScreen()->m_Route_Layer_TOP;
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else
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last_layer = GetScreen()->m_Route_Layer_BOTTOM;
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// Adjust the actual via layer pair
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switch( via->GetViaType() )
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{
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case VIA_BLIND_BURIED:
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via->SetLayerPair( first_layer, last_layer );
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break;
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case VIA_MICROVIA: // from external to the near neighbor inner layer
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{
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PCB_LAYER_ID last_inner_layer = ToLAYER_ID( ( GetBoard()->GetCopperLayerCount() - 2 ) );
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if( first_layer == B_Cu )
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last_layer = last_inner_layer;
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else if( first_layer == F_Cu )
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last_layer = In1_Cu;
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else if( first_layer == last_inner_layer )
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last_layer = B_Cu;
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else if( first_layer == In1_Cu )
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last_layer = F_Cu;
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// else error: will be removed later
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via->SetLayerPair( first_layer, last_layer );
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// Update diameter and hole size, which where set previously
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// for normal vias
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NETINFO_ITEM* net = via->GetNet();
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via->SetWidth( net->GetMicroViaSize() );
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via->SetDrill( net->GetMicroViaDrillSize() );
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}
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break;
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default:
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break;
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}
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if( Settings().m_legacyDrcOn && BAD_DRC == m_drc->Drc( via, GetBoard()->m_Track ) )
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{
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// DRC fault: the Via cannot be placed here ...
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delete via;
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m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
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// delete the track(s) added in Begin_Route()
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while( g_CurrentTrackList.GetCount() > itmp )
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{
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Delete_Segment( DC, g_CurrentTrackSegment );
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}
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SetCurItem( g_CurrentTrackSegment, false );
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// Refresh DRC diag, erased by previous calls
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if( m_drc->GetCurrentMarker() )
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SetMsgPanel( m_drc->GetCurrentMarker() );
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return false;
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}
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SetActiveLayer( last_layer );
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TRACK* lastNonVia = g_CurrentTrackSegment;
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/* A new via was created. It was Ok.
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*/
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g_CurrentTrackList.PushBack( via );
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/* The via is now in linked list and we need a new track segment
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* after the via, starting at via location.
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* it will become the new current segment (from via to the mouse cursor)
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*/
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TRACK* track = (TRACK*)lastNonVia->Clone();
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/* the above creates a new segment from the last entered segment, with the
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* current width, flags, netcode, etc... values.
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* layer, start and end point are not correct,
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* and will be modified next
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*/
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// set the layer to the new value
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track->SetLayer( GetActiveLayer() );
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/* the start point is the via position and the end point is the cursor
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* which also is on the via (will change when moving mouse)
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*/
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track->SetEnd( via->GetStart() );
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track->SetStart( via->GetStart() );
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g_CurrentTrackList.PushBack( track );
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if( Settings().m_legacyUseTwoSegmentTracks )
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{
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// Create a second segment (we must have 2 track segments to adjust)
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g_CurrentTrackList.PushBack( (TRACK*)g_CurrentTrackSegment->Clone() );
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}
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m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
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SetMsgPanel( via );
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UpdateStatusBar();
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return true;
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}
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static void ListSetState( EDA_ITEM* Start, int NbItem, STATUS_FLAGS State,
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bool onoff );
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void DrawTraces( EDA_DRAW_PANEL* panel, wxDC* DC, TRACK* aTrackList, int nbsegment,
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GR_DRAWMODE draw_mode )
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{
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// preserve the start of the list for debugging.
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for( TRACK* track = aTrackList; nbsegment > 0 && track; nbsegment--, track = track->Next() )
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{
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track->Draw( panel, DC, draw_mode );
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}
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}
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/*
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* This function try to remove an old track, when a new track is created,
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* and the old track is no more needed
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*/
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int PCB_EDIT_FRAME::EraseRedundantTrack( wxDC* aDC,
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TRACK* aNewTrack,
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int aNewTrackSegmentsCount,
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PICKED_ITEMS_LIST* aItemsListPicker )
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{
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TRACK* StartTrack, * EndTrack;
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TRACK* pt_segm;
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TRACK* pt_del;
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int ii, jj, nb_segm, nbconnect;
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wxPoint start;
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wxPoint end;
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LSET startmasklayer, endmasklayer;
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int netcode = aNewTrack->GetNetCode();
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/* Reconstruct the complete track (the new track has to start on a segment of track).
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*/
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ListSetState( aNewTrack, aNewTrackSegmentsCount, BUSY, false );
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/* If the new track begins with a via, complete the track segment using
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* the following segment as a reference because a via is often a hub of
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* segments, and does not characterize track.
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*/
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if( aNewTrack->Type() == PCB_VIA_T && ( aNewTrackSegmentsCount > 1 ) )
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aNewTrack = aNewTrack->Next();
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aNewTrack = GetBoard()->MarkTrace( aNewTrack, &aNewTrackSegmentsCount, NULL, NULL, true );
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wxASSERT( aNewTrack );
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#if 0 && defined(DEBUG)
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TRACK* EndNewTrack; // The last segment of the list chained to the track
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EndNewTrack = aNewTrack;
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for( ii = 1; ii < aNewTrackSegmentsCount; ii++ )
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{
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wxASSERT( EndNewTrack->GetState( -1 ) != 0 );
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D( printf( "track %p is newly part of net %d\n", EndNewTrack, netcode ); )
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EndNewTrack = EndNewTrack->Next();
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}
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wxASSERT( EndNewTrack->GetState( -1 ) != 0 );
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D( printf( "track %p is newly part of net %d\n", EndNewTrack, netcode ); )
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for( TRACK* track = m_Pcb->m_Track; track; track = track->Next() )
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track->Show( 0, std::cout );
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#endif
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TRACK* bufStart = m_Pcb->m_Track->GetStartNetCode( netcode ); // Beginning of tracks of the net
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TRACK* bufEnd = bufStart->GetEndNetCode( netcode ); // End of tracks of the net
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// Flags for cleaning the net.
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for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
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{
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// D( std::cout<<"track "<<pt_del<<" turning off BUSY | IN_EDIT | IS_LINKED"<<std::endl; )
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pt_del->SetState( BUSY | IN_EDIT | IS_LINKED, false );
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if( pt_del == bufEnd ) // Last segment reached
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break;
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}
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if( aNewTrack->GetEndSegments( aNewTrackSegmentsCount, &StartTrack, &EndTrack ) == 0 )
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return 0;
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if( ( StartTrack == NULL ) || ( EndTrack == NULL ) )
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return 0;
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start = StartTrack->GetStart();
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end = EndTrack->GetEnd();
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// The start and end points cannot be the same.
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if( start == end )
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return 0;
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// Determine layers interconnected these points.
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startmasklayer = StartTrack->GetLayerSet();
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endmasklayer = EndTrack->GetLayerSet();
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// There may be a via or a pad on the end points.
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pt_segm = m_Pcb->m_Track->GetVia( NULL, start, startmasklayer );
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if( pt_segm )
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startmasklayer |= pt_segm->GetLayerSet();
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if( StartTrack->start && ( StartTrack->start->Type() == PCB_PAD_T ) )
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{
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// Start on pad.
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D_PAD* pad = (D_PAD*) StartTrack->start;
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startmasklayer |= pad->GetLayerSet();
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}
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pt_segm = m_Pcb->m_Track->GetVia( NULL, end, endmasklayer );
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if( pt_segm )
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endmasklayer |= pt_segm->GetLayerSet();
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if( EndTrack->end && ( EndTrack->end->Type() == PCB_PAD_T ) )
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{
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D_PAD* pad = (D_PAD*) EndTrack->end;
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endmasklayer |= pad->GetLayerSet();
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}
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// Mark as deleted a new track (which is not involved in the search for other connections)
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ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, true );
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/* A segment must be connected to the starting point, otherwise
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* it is unnecessary to analyze the other point
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*/
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pt_segm = GetTrack( bufStart, bufEnd, start, startmasklayer );
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if( pt_segm == NULL ) // Not connected to the track starting point.
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{
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// Clear the delete flag.
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ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, false );
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return 0;
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}
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/* Marking a list of candidate segmented connect to endpoint
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* Note: the vias are not taken into account because they do
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* not define a track, since they are on an intersection.
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*/
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for( pt_del = bufStart, nbconnect = 0; ; )
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{
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pt_segm = GetTrack( pt_del, bufEnd, end, endmasklayer );
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if( pt_segm == NULL )
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break;
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if( pt_segm->Type() != PCB_VIA_T )
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{
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if( pt_segm->GetState( IS_LINKED ) == 0 )
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{
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pt_segm->SetState( IS_LINKED, true );
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nbconnect++;
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}
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}
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if( pt_del == bufEnd )
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break;
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pt_del = pt_segm->Next();
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}
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if( nbconnect == 0 )
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{
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// Clear used flags
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for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
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{
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pt_del->SetState( BUSY | IS_DELETED | IN_EDIT | IS_LINKED, false );
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if( pt_del == bufEnd ) // Last segment reached
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break;
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}
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return 0;
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}
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// Mark trace as edited (which does not involve searching for other tracks)
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ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, false );
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ListSetState( aNewTrack, aNewTrackSegmentsCount, IN_EDIT, true );
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// Test all marked segments.
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while( nbconnect )
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{
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for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
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{
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if( pt_del->GetState( IS_LINKED ) )
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break;
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if( pt_del == bufEnd ) // Last segment reached
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break;
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}
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nbconnect--;
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if( pt_del )
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pt_del->SetState( IS_LINKED, false );
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pt_del = GetBoard()->MarkTrace( pt_del, &nb_segm, NULL, NULL, true );
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/* Test if the marked track is redundant, i.e. if one of marked segments
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* is connected to the starting point of the new track.
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*/
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ii = 0;
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pt_segm = pt_del;
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for( ; pt_segm && (ii < nb_segm); pt_segm = pt_segm->Next(), ii++ )
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{
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if( pt_segm->GetState( BUSY ) == 0 )
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break;
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if( pt_segm->GetStart() == start || pt_segm->GetEnd() == start )
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{
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// Marked track can be erased.
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TRACK* NextS;
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DrawTraces( m_canvas, aDC, pt_del, nb_segm, GR_XOR | GR_HIGHLIGHT );
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for( jj = 0; jj < nb_segm; jj++, pt_del = NextS )
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{
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NextS = pt_del->Next();
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if( aItemsListPicker )
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{
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pt_del->UnLink();
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pt_del->SetStatus( 0 );
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pt_del->ClearFlags();
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GetBoard()->GetConnectivity()->Remove( pt_del );
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ITEM_PICKER picker( pt_del, UR_DELETED );
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aItemsListPicker->PushItem( picker );
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}
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else
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{
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GetBoard()->GetConnectivity()->Remove( pt_del );
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pt_del->DeleteStructure();
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}
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}
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// Clean up flags.
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for( pt_del = m_Pcb->m_Track; pt_del != NULL; pt_del = pt_del->Next() )
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{
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if( pt_del->GetState( IN_EDIT ) )
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{
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pt_del->SetState( IN_EDIT, false );
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if( aDC )
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pt_del->Draw( m_canvas, aDC, GR_OR );
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}
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pt_del->SetState( IN_EDIT | IS_LINKED, false );
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}
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return 1;
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}
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}
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// Clear BUSY flag here because the track did not get marked.
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ListSetState( pt_del, nb_segm, BUSY, false );
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}
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// Clear used flags
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for( pt_del = m_Pcb->m_Track; pt_del; pt_del = pt_del->Next() )
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{
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pt_del->SetState( BUSY | IS_DELETED | IN_EDIT | IS_LINKED, false );
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if( pt_del == bufEnd ) // Last segment reached
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break;
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}
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return 0;
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}
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/* Set the bits of .m_State member to on/off value, using bit mask State
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* of a list of EDA_ITEM
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*/
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static void ListSetState( EDA_ITEM* Start, int NbItem, STATUS_FLAGS State,
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bool onoff )
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{
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for( ; (Start != NULL ) && ( NbItem > 0 ); NbItem--, Start = Start->Next() )
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{
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Start->SetState( State, onoff );
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}
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}
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