354 lines
13 KiB
C++
354 lines
13 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <pcb_shape.h>
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#include <footprint.h>
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#include <geometry/seg.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include "drc_rtree.h"
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/*
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Board edge clearance test. Checks all items for their mechanical clearances against the board
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edge.
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Errors generated:
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- DRCE_EDGE_CLEARANCE
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- DRCE_SILK_EDGE_CLEARANCE
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TODO:
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- separate holes to edge check
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- tester only looks for edge crossings. it doesn't check if items are inside/outside the board
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area.
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- pad test missing!
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*/
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class DRC_TEST_PROVIDER_EDGE_CLEARANCE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
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{
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public:
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DRC_TEST_PROVIDER_EDGE_CLEARANCE () :
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DRC_TEST_PROVIDER_CLEARANCE_BASE(),
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m_largestEdgeClearance( 0 )
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{
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}
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virtual ~DRC_TEST_PROVIDER_EDGE_CLEARANCE()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "edge_clearance" );
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}
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests items vs board edge clearance" );
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}
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private:
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bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other,
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DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode );
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private:
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std::vector<PAD*> m_castellatedPads;
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int m_largestEdgeClearance;
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};
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bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape,
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BOARD_ITEM* edge,
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DRC_CONSTRAINT_T aConstraintType,
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PCB_DRC_CODE aErrorCode )
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{
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std::shared_ptr<SHAPE> shape;
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if( edge->Type() == PCB_PAD_T )
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shape = edge->GetEffectiveHoleShape();
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else
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shape = edge->GetEffectiveShape( Edge_Cuts );
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auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, UNDEFINED_LAYER );
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int minClearance = constraint.GetValue().Min();
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int actual;
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VECTOR2I pos;
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
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{
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if( itemShape->Collide( shape.get(), minClearance, &actual, &pos ) )
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{
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// Exact clearance is allowed
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if( minClearance > 0 && actual == minClearance )
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return true;
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if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
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{
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// Edge collisions are allowed inside the holes of castellated pads
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for( PAD* castellatedPad : m_castellatedPads )
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{
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if( castellatedPad->GetEffectiveHoleShape()->Collide( pos ) )
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return true;
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}
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}
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
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// Only report clearance info if there is any; otherwise it's just a straight collision
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if( minClearance > 0 )
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{
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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minClearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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}
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drce->SetItems( edge->m_Uuid, item->m_Uuid );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, Edge_Cuts );
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return false; // don't report violations with multiple edges; one is enough
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}
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}
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return true;
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}
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bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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{
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_EDGE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper to board edge clearances..." ) ) )
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return false; // DRC cancelled
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}
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else if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_EDGE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking silk to board edge clearances..." ) ) )
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return false; // DRC cancelled
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}
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else
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{
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reportAux( wxT( "Edge clearance violations ignored. Tests not run." ) );
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return true; // continue with other tests
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}
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m_board = m_drcEngine->GetBoard();
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m_castellatedPads.clear();
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DRC_CONSTRAINT worstClearanceConstraint;
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if( m_drcEngine->QueryWorstConstraint( EDGE_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
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m_largestEdgeClearance = worstClearanceConstraint.GetValue().Min();
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reportAux( wxT( "Worst clearance : %d nm" ), m_largestEdgeClearance );
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/*
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* Build an RTree of the various edges (including NPTH holes) and margins found on the board.
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*/
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std::vector<std::unique_ptr<PCB_SHAPE>> edges;
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DRC_RTREE edgesTree;
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forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ),
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[&]( BOARD_ITEM *item ) -> bool
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{
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PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
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STROKE_PARAMS stroke = shape->GetStroke();
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if( item->IsOnLayer( Edge_Cuts ) )
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stroke.SetWidth( 0 );
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if( shape->GetShape() == SHAPE_T::RECT && !shape->IsFilled() )
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{
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// A single rectangle for the board would make the RTree useless, so convert
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// to 4 edges
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetEndX( shape->GetStartX() );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetEndY( shape->GetStartY() );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStartX( shape->GetEndX() );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStartY( shape->GetEndY() );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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}
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else if( shape->GetShape() == SHAPE_T::POLY && !shape->IsFilled() )
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{
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// A single polygon for the board would make the RTree useless, so convert
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// to n edges.
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SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
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for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
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{
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SEG seg = poly.CSegment( ii );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStart( seg.A );
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edges.back()->SetEnd( seg.B );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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}
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}
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else
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{
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetStroke( stroke );
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edges.back()->SetParentGroup( nullptr );
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}
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return true;
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} );
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for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
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{
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for( PCB_LAYER_ID layer : { Edge_Cuts, Margin } )
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{
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if( edge->IsOnLayer( layer ) )
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edgesTree.Insert( edge.get(), layer, m_largestEdgeClearance );
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}
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}
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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if( pad->GetAttribute() == PAD_ATTRIB::NPTH && pad->HasHole() )
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{
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// edge-clearances are for milling tolerances (drilling tolerances are handled
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// by hole-clearances)
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if( pad->GetDrillSizeX() != pad->GetDrillSizeY() )
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edgesTree.Insert( pad, Edge_Cuts, m_largestEdgeClearance );
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}
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if( pad->GetProperty() == PAD_PROP::CASTELLATED )
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m_castellatedPads.push_back( pad );
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}
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}
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/*
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* Test copper and silk items against the set of edges.
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*/
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const int progressDelta = 200;
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int count = 0;
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int ii = 0;
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forEachGeometryItem( s_allBasicItemsButZones, LSET::AllLayersMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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count++;
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return true;
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} );
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forEachGeometryItem( s_allBasicItemsButZones, LSET::AllLayersMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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bool testCopper = !m_drcEngine->IsErrorLimitExceeded( DRCE_EDGE_CLEARANCE );
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bool testSilk = !m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_EDGE_CLEARANCE );
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if( !testCopper && !testSilk )
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return false; // All limits exceeded; we're done
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if( !reportProgress( ii++, count, progressDelta ) )
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return false; // DRC cancelled; we're done
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if( isInvisibleText( item ) )
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return true; // Continue with other items
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if( item->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( item );
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if( pad->GetProperty() == PAD_PROP::CASTELLATED
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|| pad->GetAttribute() == PAD_ATTRIB::CONN )
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{
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return true; // Continue with other items
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}
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}
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const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape();
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for( PCB_LAYER_ID testLayer : { Edge_Cuts, Margin } )
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{
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if( testCopper && item->IsOnCopperLayer() )
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{
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edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
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[&]( BOARD_ITEM* edge ) -> bool
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{
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return testAgainstEdge( item, itemShape.get(), edge,
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EDGE_CLEARANCE_CONSTRAINT,
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DRCE_EDGE_CLEARANCE );
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},
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m_largestEdgeClearance );
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}
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if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
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{
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if( edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
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[&]( BOARD_ITEM* edge ) -> bool
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{
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return testAgainstEdge( item, itemShape.get(), edge,
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SILK_CLEARANCE_CONSTRAINT,
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DRCE_SILK_EDGE_CLEARANCE );
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},
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m_largestEdgeClearance ) )
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{
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// violations reported during QueryColliding
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}
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else
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{
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// TODO: check postion being outside board boundary
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}
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}
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}
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return true;
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} );
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reportRuleStatistics();
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_EDGE_CLEARANCE> dummy;
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}
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