686 lines
21 KiB
C++
686 lines
21 KiB
C++
/*******************************************/
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/* class_board.cpp - BOARD class functions */
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/*******************************************/
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#include "fctsys.h"
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#include "common.h"
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#include "pcbnew.h"
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#include "bitmaps.h"
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/*****************/
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/* Class BOARD: */
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/*****************/
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/* Constructor */
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BOARD::BOARD( EDA_BaseStruct* parent, WinEDA_BasePcbFrame* frame ) :
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BOARD_ITEM( (BOARD_ITEM*) parent, TYPEPCB )
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{
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m_PcbFrame = frame;
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m_Status_Pcb = 0; // Mot d'etat: Bit 1 = Chevelu calcule
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m_NbNets = 0; // Nombre de nets (equipotentielles)
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m_BoardSettings = &g_DesignSettings;
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m_NbPads = 0; // nombre total de pads
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m_NbNodes = 0; // nombre de pads connectes
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m_NbLinks = 0; // nombre de chevelus (donc aussi nombre
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// minimal de pistes a tracer
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m_NbSegmTrack = 0; // nombre d'elements de type segments de piste
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m_NbSegmZone = 0; // nombre d'elements de type segments de zone
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m_NbNoconnect = 0; // nombre de chevelus actifs
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m_NbLoclinks = 0; // nb ratsnest local
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m_Drawings = NULL; // pointeur sur liste drawings
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m_Modules = NULL; // pointeur sur liste zone modules
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m_Equipots = NULL; // pointeur liste zone equipot
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m_Track = NULL; // pointeur relatif zone piste
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m_Zone = NULL; // pointeur tableau zone zones de cuivre
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m_Pads = NULL; // pointeur liste d'acces aux pads
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m_Ratsnest = NULL; // pointeur liste rats
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m_LocalRatsnest = NULL; // pointeur liste rats local
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m_CurrentLimitZone = NULL; // pointeur liste des EDEGE_ZONES
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// de determination des contours de zone
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}
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/***************/
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/* Destructeur */
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/***************/
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BOARD::~BOARD()
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{
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m_Drawings->DeleteStructList();
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m_Drawings = 0;
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m_Modules->DeleteStructList();
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m_Modules = 0;
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m_Equipots->DeleteStructList();
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m_Equipots = 0;
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m_Track->DeleteStructList();
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m_Track = 0;
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m_Zone->DeleteStructList();
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m_Zone = 0;
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m_CurrentLimitZone->DeleteStructList();
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m_CurrentLimitZone = 0;
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MyFree( m_Pads );
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m_Pads = 0;
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MyFree( m_Ratsnest );
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m_Ratsnest = 0;
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MyFree( m_LocalRatsnest );
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m_LocalRatsnest = 0;
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}
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void BOARD::UnLink()
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{
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/* Modification du chainage arriere */
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if( Pback )
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{
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if( Pback->Type() == TYPEPCB )
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{
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Pback->Pnext = Pnext;
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}
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else /* Le chainage arriere pointe sur la structure "Pere" */
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{
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// Pback-> = Pnext;
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}
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}
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/* Modification du chainage avant */
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if( Pnext )
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Pnext->Pback = Pback;
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Pnext = Pback = NULL;
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}
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/* Routines de calcul des nombres de segments pistes et zones */
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int BOARD::GetNumSegmTrack()
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{
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TRACK* CurTrack = m_Track;
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int ii = 0;
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for( ; CurTrack != NULL; CurTrack = (TRACK*) CurTrack->Pnext )
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ii++;
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m_NbSegmTrack = ii;
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return ii;
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}
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int BOARD::GetNumSegmZone()
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{
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TRACK* CurTrack = m_Zone;
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int ii = 0;
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for( ; CurTrack != NULL; CurTrack = (TRACK*) CurTrack->Pnext )
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ii++;
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m_NbSegmZone = ii;
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return ii;
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}
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// retourne le nombre de connexions manquantes
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int BOARD::GetNumNoconnect()
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{
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return m_NbNoconnect;
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}
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// retourne le nombre de chevelus
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int BOARD::GetNumRatsnests()
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{
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return m_NbLinks;
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}
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// retourne le nombre de pads a netcode > 0
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int BOARD::GetNumNodes()
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{
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return m_NbNodes;
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}
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/***********************************/
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bool BOARD::ComputeBoundaryBox()
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/***********************************/
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/* Determine le rectangle d'encadrement du pcb
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* Ce rectangle englobe les contours pcb, pads , vias et piste
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* Sortie:
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* m_PcbBox
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*
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* retourne:
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* 0 si aucun element utile
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* 1 sinon
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*/
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{
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int rayon, cx, cy, d, xmin, ymin, xmax, ymax;
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bool Has_Items = FALSE;
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EDA_BaseStruct* PtStruct;
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DRAWSEGMENT* ptr;
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TRACK* Track;
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xmin = ymin = 0x7FFFFFFFl;
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xmax = ymax = -0x7FFFFFFFl;
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/* Analyse des Contours PCB */
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PtStruct = m_Drawings;
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for( ; PtStruct != NULL; PtStruct = PtStruct->Pnext )
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{
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if( PtStruct->Type() != TYPEDRAWSEGMENT )
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continue;
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ptr = (DRAWSEGMENT*) PtStruct;
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d = (ptr->m_Width / 2) + 1;
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if( ptr->m_Shape == S_CIRCLE )
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{
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cx = ptr->m_Start.x; cy = ptr->m_Start.y;
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rayon = (int) hypot( (double) (ptr->m_End.x - cx), (double) (ptr->m_End.y - cy) );
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rayon += d;
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xmin = MIN( xmin, cx - rayon );
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ymin = MIN( ymin, cy - rayon );
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xmax = MAX( xmax, cx + rayon );
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ymax = MAX( ymax, cy + rayon );
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Has_Items = TRUE;
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}
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else
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{
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cx = MIN( ptr->m_Start.x, ptr->m_End.x );
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cy = MIN( ptr->m_Start.y, ptr->m_End.y );
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xmin = MIN( xmin, cx - d );
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ymin = MIN( ymin, cy - d );
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cx = MAX( ptr->m_Start.x, ptr->m_End.x );
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cy = MAX( ptr->m_Start.y, ptr->m_End.y );
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xmax = MAX( xmax, cx + d );
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ymax = MAX( ymax, cy + d );
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Has_Items = TRUE;
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}
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}
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/* Analyse des Modules */
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MODULE* module = m_Modules;
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for( ; module != NULL; module = (MODULE*) module->Pnext )
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{
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Has_Items = TRUE;
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xmin = MIN( xmin, ( module->m_Pos.x + module->m_BoundaryBox.GetX() ) );
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ymin = MIN( ymin, ( module->m_Pos.y + module->m_BoundaryBox.GetY() ) );
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xmax = MAX( xmax, module->m_Pos.x + module->m_BoundaryBox.GetRight() );
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ymax = MAX( ymax, module->m_Pos.y + module->m_BoundaryBox.GetBottom() );
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D_PAD* pt_pad = module->m_Pads;
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for( ; pt_pad != NULL; pt_pad = (D_PAD*) pt_pad->Pnext )
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{
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d = pt_pad->m_Rayon;
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xmin = MIN( xmin, pt_pad->m_Pos.x - d );
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ymin = MIN( ymin, pt_pad->m_Pos.y - d );
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xmax = MAX( xmax, pt_pad->m_Pos.x + d );
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ymax = MAX( ymax, pt_pad->m_Pos.y + d );
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}
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}
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/* Analyse des segments de piste et zone*/
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for( Track = m_Track; Track != NULL; Track = (TRACK*) Track->Pnext )
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{
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d = (Track->m_Width / 2) + 1;
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cx = MIN( Track->m_Start.x, Track->m_End.x );
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cy = MIN( Track->m_Start.y, Track->m_End.y );
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xmin = MIN( xmin, cx - d );
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ymin = MIN( ymin, cy - d );
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cx = MAX( Track->m_Start.x, Track->m_End.x );
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cy = MAX( Track->m_Start.y, Track->m_End.y );
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xmax = MAX( xmax, cx + d );
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ymax = MAX( ymax, cy + d );
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Has_Items = TRUE;
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}
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for( Track = m_Zone; Track != NULL; Track = (TRACK*) Track->Pnext )
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{
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d = (Track->m_Width / 2) + 1;
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cx = MIN( Track->m_Start.x, Track->m_End.x );
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cy = MIN( Track->m_Start.y, Track->m_End.y );
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xmin = MIN( xmin, cx - d );
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ymin = MIN( ymin, cy - d );
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cx = MAX( Track->m_Start.x, Track->m_End.x );
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cy = MAX( Track->m_Start.y, Track->m_End.y );
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xmax = MAX( xmax, cx + d );
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ymax = MAX( ymax, cy + d );
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Has_Items = TRUE;
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}
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if( !Has_Items && m_PcbFrame )
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{
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if( m_PcbFrame->m_Draw_Sheet_Ref )
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{
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xmin = ymin = 0;
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xmax = m_PcbFrame->m_CurrentScreen->ReturnPageSize().x;
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ymax = m_PcbFrame->m_CurrentScreen->ReturnPageSize().y;
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}
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else
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{
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xmin = -m_PcbFrame->m_CurrentScreen->ReturnPageSize().x / 2;
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ymin = -m_PcbFrame->m_CurrentScreen->ReturnPageSize().y / 2;
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xmax = m_PcbFrame->m_CurrentScreen->ReturnPageSize().x / 2;
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ymax = m_PcbFrame->m_CurrentScreen->ReturnPageSize().y / 2;
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}
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}
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m_BoundaryBox.SetX( xmin );
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m_BoundaryBox.SetY( ymin );
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m_BoundaryBox.SetWidth( xmax - xmin );
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m_BoundaryBox.SetHeight( ymax - ymin );
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return Has_Items;
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}
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// virtual, see pcbstruct.h
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void BOARD::Display_Infos( WinEDA_DrawFrame* frame )
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{
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/* Affiche l'etat du PCB : nb de pads, nets , connexions.. */
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#define POS_AFF_NBPADS 1
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#define POS_AFF_NBVIAS 8
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#define POS_AFF_NBNODES 16
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#define POS_AFF_NBLINKS 24
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#define POS_AFF_NBNETS 32
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#define POS_AFF_NBCONNECT 40
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#define POS_AFF_NBNOCONNECT 48
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int nb_vias = 0, ii;
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EDA_BaseStruct* Struct;
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wxString txt;
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frame->MsgPanel->EraseMsgBox();
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txt.Printf( wxT( "%d" ), m_NbPads );
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Affiche_1_Parametre( frame, POS_AFF_NBPADS, _( "Pads" ), txt, DARKGREEN );
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for( ii = 0, Struct = m_Track; Struct != NULL; Struct = Struct->Pnext )
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{
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ii++;
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if( Struct->Type() == TYPEVIA )
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nb_vias++;
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}
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txt.Printf( wxT( "%d" ), nb_vias );
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Affiche_1_Parametre( frame, POS_AFF_NBVIAS, _( "Vias" ), txt, DARKGREEN );
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txt.Printf( wxT( "%d" ), GetNumNodes() );
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Affiche_1_Parametre( frame, POS_AFF_NBNODES, _( "Nodes" ), txt, DARKCYAN );
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txt.Printf( wxT( "%d" ), m_NbLinks );
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Affiche_1_Parametre( frame, POS_AFF_NBLINKS, _( "Links" ), txt, DARKGREEN );
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txt.Printf( wxT( "%d" ), m_NbNets );
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Affiche_1_Parametre( frame, POS_AFF_NBNETS, _( "Nets" ), txt, RED );
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txt.Printf( wxT( "%d" ), m_NbLinks - GetNumNoconnect() );
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Affiche_1_Parametre( frame, POS_AFF_NBCONNECT, _( "Connect" ), txt, DARKGREEN );
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txt.Printf( wxT( "%d" ), GetNumNoconnect() );
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Affiche_1_Parametre( frame, POS_AFF_NBNOCONNECT, _( "NoConn" ), txt, BLUE );
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}
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// virtual, see pcbstruct.h
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SEARCH_RESULT BOARD::Visit( INSPECTOR* inspector, const void* testData,
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const KICAD_T scanTypes[] )
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{
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KICAD_T stype;
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SEARCH_RESULT result = SEARCH_CONTINUE;
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const KICAD_T* p = scanTypes;
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bool done=false;
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#if 0 && defined(DEBUG)
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std::cout << GetClass().mb_str() << ' ';
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#endif
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while( !done )
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{
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stype = *p;
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switch( stype )
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{
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case TYPEPCB:
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result = inspector->Inspect( this, testData ); // inspect me
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// skip over any types handled in the above call.
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++p;
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break;
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/* Instances of the requested KICAD_T live in a list, either one
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that I manage, or that my modules manage. If it's a type managed
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by class MODULE, then simply pass it on to each module's
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MODULE::Visit() function by way of the
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IterateForward( m_Modules, ... ) call.
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*/
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case TYPEMODULE:
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case TYPEPAD:
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case TYPETEXTEMODULE:
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case TYPEEDGEMODULE:
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// this calls MODULE::Visit() on each module.
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result = IterateForward( m_Modules, inspector, testData, p );
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// skip over any types handled in the above call.
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for(;;)
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{
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switch( stype = *++p )
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{
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case TYPEMODULE:
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case TYPEPAD:
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case TYPETEXTEMODULE:
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case TYPEEDGEMODULE:
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continue;
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default:;
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}
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break;
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}
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break;
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case TYPEDRAWSEGMENT:
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case TYPETEXTE:
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case TYPEMARQUEUR:
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case TYPECOTATION:
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case TYPEMIRE:
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result = IterateForward( m_Drawings, inspector, testData, p );
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// skip over any types handled in the above call.
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for(;;)
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{
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switch( stype = *++p )
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{
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case TYPEDRAWSEGMENT:
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case TYPETEXTE:
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case TYPEMARQUEUR:
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case TYPECOTATION:
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case TYPEMIRE:
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continue;
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default:;
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}
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break;
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}
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;
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break;
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#if 0 // both these are on same list, so we must scan it twice in order to get VIA priority,
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// using new #else code below.
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// But we are not using separte lists for TRACKs and SEGVIAs, because items are ordered (sortered) in the linked
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// list by netcode AND by physical distance:
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// when created, if a track or via is connected to an existing track or via, it is put in linked list
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// after this existing track or via
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// So usually, connected tracks or vias are grouped in this list
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// So the algorithm (used in rastnest computations) which computes the track connectivity is faster (more than 100 time regarding to
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// a non ordered list) because when it searchs for a connexion, first it tests the near (near in term of linked list) 50 items
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// from the current item (track or via) in test.
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// Usually, because of this sort, a connected item (if exists) is found.
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// If not found (and only in this case) an exhaustive (and time consumming) search is made,
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// but this case is statistically rare.
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case TYPEVIA:
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case TYPETRACK:
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result = IterateForward( m_Track, inspector, testData, p );
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// skip over any types handled in the above call.
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for(;;)
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{
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switch( stype = *++p )
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{
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case TYPEVIA:
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case TYPETRACK:
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continue;
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default:;
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}
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break;
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}
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break;
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#else
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case TYPEVIA:
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result = IterateForward( m_Track, inspector, testData, p );
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++p;
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break;
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case TYPETRACK:
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result = IterateForward( m_Track, inspector, testData, p );
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++p;
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break;
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#endif
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case PCB_EQUIPOT_STRUCT_TYPE:
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result = IterateForward( m_Equipots, inspector, testData, p );
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++p;
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break;
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case TYPEZONE:
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result = IterateForward( m_Zone, inspector, testData, p );
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++p;
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break;
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case TYPEEDGEZONE:
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result = IterateForward( m_CurrentLimitZone, inspector, testData, p );
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++p;
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break;
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default: // catch EOT or ANY OTHER type here and return.
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done = true;
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break;
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}
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if( result == SEARCH_QUIT )
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break;
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}
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return result;
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}
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/* now using PcbGeneralLocateAndDisplay()
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// see pcbstruct.h
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BOARD_ITEM* BOARD::FindPadOrModule( const wxPoint& refPos, int layer )
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{
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class PadOrModule : public INSPECTOR
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{
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public:
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BOARD_ITEM* found;
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int layer;
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int layer_mask;
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PadOrModule( int alayer ) :
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found(0), layer(alayer), layer_mask( g_TabOneLayerMask[alayer] )
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{}
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SEARCH_RESULT Inspect( EDA_BaseStruct* testItem, const void* testData )
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{
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BOARD_ITEM* item = (BOARD_ITEM*) testItem;
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const wxPoint& refPos = *(const wxPoint*) testData;
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if( item->Type() == TYPEPAD )
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{
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D_PAD* pad = (D_PAD*) item;
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if( pad->HitTest( refPos ) )
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{
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if( layer_mask & pad->m_Masque_Layer )
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{
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found = item;
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return SEARCH_QUIT;
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}
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else if( !found )
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{
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MODULE* parent = (MODULE*) pad->m_Parent;
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if( IsModuleLayerVisible( parent->GetLayer() ) )
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found = item;
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}
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}
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|
}
|
|
|
|
else if( item->Type() == TYPEMODULE )
|
|
{
|
|
MODULE* module = (MODULE*) item;
|
|
|
|
// consider only visible modules
|
|
if( IsModuleLayerVisible( module->GetLayer() ) )
|
|
{
|
|
if( module->HitTest( refPos ) )
|
|
{
|
|
if( layer == module->GetLayer() )
|
|
{
|
|
found = item;
|
|
return SEARCH_QUIT;
|
|
}
|
|
|
|
// layer mismatch, save in case we don't find a
|
|
// future layer match hit.
|
|
if( !found )
|
|
found = item;
|
|
}
|
|
}
|
|
}
|
|
return SEARCH_CONTINUE;
|
|
}
|
|
};
|
|
|
|
PadOrModule inspector( layer );
|
|
|
|
// search only for PADs first, then MODULES, and preferably a layer match
|
|
static const KICAD_T scanTypes[] = { TYPEPAD, TYPEMODULE, EOT };
|
|
|
|
// visit this BOARD with the above inspector
|
|
Visit( &inspector, &refPos, scanTypes );
|
|
|
|
return inspector.found;
|
|
}
|
|
*/
|
|
|
|
|
|
/**
|
|
* Function FindNet
|
|
* searches for a net with the given netcode.
|
|
* @param anetcode The netcode to search for.
|
|
* @return EQUIPOT* - the net or NULL if not found.
|
|
*/
|
|
EQUIPOT* BOARD::FindNet( int anetcode ) const
|
|
{
|
|
if( anetcode <= 0 )
|
|
return NULL;
|
|
|
|
EQUIPOT* net = (EQUIPOT*) m_Equipots;
|
|
while( net )
|
|
{
|
|
if( net->GetNet() == anetcode )
|
|
break;
|
|
net = (EQUIPOT*) net->Pnext;
|
|
}
|
|
return net;
|
|
}
|
|
|
|
|
|
#if defined(DEBUG)
|
|
|
|
/**
|
|
* Function Show
|
|
* is used to output the object tree, currently for debugging only.
|
|
* @param nestLevel An aid to prettier tree indenting, and is the level
|
|
* of nesting of this object within the overall tree.
|
|
* @param os The ostream& to output to.
|
|
*/
|
|
void BOARD::Show( int nestLevel, std::ostream& os )
|
|
{
|
|
EDA_BaseStruct* p;
|
|
|
|
// for now, make it look like XML:
|
|
NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() << ">\n";
|
|
|
|
// specialization of the output:
|
|
NestedSpace( nestLevel+1, os ) << "<modules>\n";
|
|
p = m_Modules;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</modules>\n";
|
|
|
|
NestedSpace( nestLevel+1, os ) << "<pdrawings>\n";
|
|
p = m_Drawings;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</pdrawings>\n";
|
|
|
|
NestedSpace( nestLevel+1, os ) << "<nets>\n";
|
|
p = m_Equipots;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</nets>\n";
|
|
|
|
NestedSpace( nestLevel+1, os ) << "<tracks>\n";
|
|
p = m_Track;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</tracks>\n";
|
|
|
|
NestedSpace( nestLevel+1, os ) << "<zones>\n";
|
|
p = m_Zone;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</zones>\n";
|
|
|
|
NestedSpace( nestLevel+1, os ) << "<edgezones>\n";
|
|
p = m_CurrentLimitZone;
|
|
for( ; p; p = p->Pnext )
|
|
p->Show( nestLevel+2, os );
|
|
NestedSpace( nestLevel+1, os ) << "</edgezones>\n";
|
|
|
|
p = m_Son;
|
|
for( ; p; p = p->Pnext )
|
|
{
|
|
p->Show( nestLevel+1, os );
|
|
}
|
|
|
|
NestedSpace( nestLevel, os ) << "</" << GetClass().Lower().mb_str() << ">\n";
|
|
}
|
|
|
|
|
|
/* wrote this before discovering ReturnPcbLayerName()
|
|
const char* BOARD::ShowLayer( int aLayer )
|
|
{
|
|
const char* rs;
|
|
|
|
switch( aLayer )
|
|
{
|
|
case LAYER_COPPER_LAYER_N: rs = "cu"; break;
|
|
case LAYER_N_2: rs = "layer2"; break;
|
|
case LAYER_N_3: rs = "layer3"; break;
|
|
case LAYER_N_4: rs = "layer4"; break;
|
|
case LAYER_N_5: rs = "layer5"; break;
|
|
case LAYER_N_6: rs = "layer6"; break;
|
|
case LAYER_N_7: rs = "layer7"; break;
|
|
case LAYER_N_8: rs = "layer8"; break;
|
|
case LAYER_N_9: rs = "layer9"; break;
|
|
case LAYER_N_10: rs = "layer10"; break;
|
|
case LAYER_N_11: rs = "layer11"; break;
|
|
case LAYER_N_12: rs = "layer12"; break;
|
|
case LAYER_N_13: rs = "layer13"; break;
|
|
case LAYER_N_14: rs = "layer14"; break;
|
|
case LAYER_N_15: rs = "layer15"; break;
|
|
case LAYER_CMP_N: rs = "cmp"; break;
|
|
case ADHESIVE_N_CU: rs = "cu/adhesive"; break;
|
|
case ADHESIVE_N_CMP: rs = "cmp/adhesive"; break;
|
|
case SOLDERPASTE_N_CU: rs = "cu/sldrpaste"; break;
|
|
case SOLDERPASTE_N_CMP: rs = "cmp/sldrpaste"; break;
|
|
case SILKSCREEN_N_CU: rs = "cu/silkscreen"; break;
|
|
case SILKSCREEN_N_CMP: rs = "cmp/silkscreen"; break;
|
|
case SOLDERMASK_N_CU: rs = "cu/sldrmask"; break;
|
|
case SOLDERMASK_N_CMP: rs = "cmp/sldrmask"; break;
|
|
case DRAW_N: rs = "drawing"; break;
|
|
case COMMENT_N: rs = "comment"; break;
|
|
case ECO1_N: rs = "eco_1"; break;
|
|
case ECO2_N: rs = "eco_2"; break;
|
|
case EDGE_N: rs = "edge"; break;
|
|
default: rs = "???"; break;
|
|
}
|
|
|
|
return rs;
|
|
}
|
|
*/
|
|
|
|
#endif
|