351 lines
9.0 KiB
C++
351 lines
9.0 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2020-2021 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_test_provider.h>
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#include <pcb_track.h>
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#include <footprint.h>
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#include <pad.h>
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#include <zone.h>
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#include <pcb_text.h>
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// A list of all basic (ie: non-compound) board geometry items
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std::vector<KICAD_T> DRC_TEST_PROVIDER::s_allBasicItems;
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std::vector<KICAD_T> DRC_TEST_PROVIDER::s_allBasicItemsButZones;
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DRC_TEST_PROVIDER_REGISTRY::~DRC_TEST_PROVIDER_REGISTRY()
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{
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for( DRC_TEST_PROVIDER* provider : m_providers )
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delete provider;
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}
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DRC_TEST_PROVIDER::DRC_TEST_PROVIDER() :
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m_drcEngine( nullptr )
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{
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}
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const wxString DRC_TEST_PROVIDER::GetName() const { return "<no name test>"; }
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const wxString DRC_TEST_PROVIDER::GetDescription() const { return ""; }
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void DRC_TEST_PROVIDER::reportViolation( std::shared_ptr<DRC_ITEM>& item,
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const wxPoint& aMarkerPos, PCB_LAYER_ID aMarkerLayer )
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{
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if( item->GetViolatingRule() )
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accountCheck( item->GetViolatingRule() );
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item->SetViolatingTest( this );
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m_drcEngine->ReportViolation( item, aMarkerPos, aMarkerLayer );
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}
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bool DRC_TEST_PROVIDER::reportProgress( int aCount, int aSize, int aDelta )
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{
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if( ( aCount % aDelta ) == 0 || aCount == aSize - 1 )
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{
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if( !m_drcEngine->ReportProgress( (double) aCount / (double) aSize ) )
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return false;
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}
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return true;
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}
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bool DRC_TEST_PROVIDER::reportPhase( const wxString& aMessage )
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{
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reportAux( aMessage );
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return m_drcEngine->ReportPhase( aMessage );
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}
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void DRC_TEST_PROVIDER::reportAux( wxString fmt, ... )
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{
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va_list vargs;
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va_start( vargs, fmt );
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wxString str;
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str.PrintfV( fmt, vargs );
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va_end( vargs );
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m_drcEngine->ReportAux( str );
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}
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EDA_UNITS DRC_TEST_PROVIDER::userUnits() const
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{
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return m_drcEngine->UserUnits();
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}
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void DRC_TEST_PROVIDER::accountCheck( const DRC_RULE* ruleToTest )
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{
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auto it = m_stats.find( ruleToTest );
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if( it == m_stats.end() )
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m_stats[ ruleToTest ] = 1;
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else
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m_stats[ ruleToTest ] += 1;
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}
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void DRC_TEST_PROVIDER::accountCheck( const DRC_CONSTRAINT& constraintToTest )
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{
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accountCheck( constraintToTest.GetParentRule() );
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}
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void DRC_TEST_PROVIDER::reportRuleStatistics()
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{
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if( !m_isRuleDriven )
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return;
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m_drcEngine->ReportAux( "Rule hit statistics: " );
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for( const std::pair<const DRC_RULE* const, int>& stat : m_stats )
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{
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if( stat.first )
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{
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m_drcEngine->ReportAux( wxString::Format( " - rule '%s': %d hits ",
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stat.first->m_Name,
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stat.second ) );
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}
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}
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}
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int DRC_TEST_PROVIDER::forEachGeometryItem( const std::vector<KICAD_T>& aTypes, LSET aLayers,
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const std::function<bool( BOARD_ITEM*)>& aFunc )
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{
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BOARD *brd = m_drcEngine->GetBoard();
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std::bitset<MAX_STRUCT_TYPE_ID> typeMask;
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int n = 0;
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if( s_allBasicItems.size() == 0 )
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{
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for( int i = 0; i < MAX_STRUCT_TYPE_ID; i++ )
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{
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if( i != PCB_FOOTPRINT_T && i != PCB_GROUP_T )
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{
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s_allBasicItems.push_back( (KICAD_T) i );
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if( i != PCB_ZONE_T && i != PCB_FP_ZONE_T )
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s_allBasicItemsButZones.push_back( (KICAD_T) i );
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}
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}
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}
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if( aTypes.size() == 0 )
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{
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for( int i = 0; i < MAX_STRUCT_TYPE_ID; i++ )
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typeMask[ i ] = true;
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}
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else
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{
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for( KICAD_T aType : aTypes )
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typeMask[ aType ] = true;
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}
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for( PCB_TRACK* item : brd->Tracks() )
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{
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if( (item->GetLayerSet() & aLayers).any() )
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{
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if( typeMask[ PCB_TRACE_T ] && item->Type() == PCB_TRACE_T )
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{
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aFunc( item );
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n++;
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}
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else if( typeMask[ PCB_VIA_T ] && item->Type() == PCB_VIA_T )
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{
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aFunc( item );
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n++;
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}
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else if( typeMask[ PCB_ARC_T ] && item->Type() == PCB_ARC_T )
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{
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aFunc( item );
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n++;
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}
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}
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}
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for( BOARD_ITEM* item : brd->Drawings() )
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{
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if( (item->GetLayerSet() & aLayers).any() )
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{
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if( typeMask[ PCB_DIMENSION_T ] && BaseType( item->Type() ) == PCB_DIMENSION_T )
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{
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if( !aFunc( item ) )
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return n;
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n++;
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}
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else if( typeMask[ PCB_SHAPE_T ] && item->Type() == PCB_SHAPE_T )
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{
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if( !aFunc( item ) )
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return n;
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n++;
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}
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else if( typeMask[ PCB_TEXT_T ] && item->Type() == PCB_TEXT_T )
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{
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if( !aFunc( item ) )
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return n;
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n++;
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}
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else if( typeMask[ PCB_TARGET_T ] && item->Type() == PCB_TARGET_T )
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{
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if( !aFunc( item ) )
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return n;
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n++;
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}
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}
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}
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if( typeMask[ PCB_ZONE_T ] )
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{
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for( ZONE* item : brd->Zones() )
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{
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if( ( item->GetLayerSet() & aLayers ).any() )
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{
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if( !aFunc( item ) )
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return n;
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n++;
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}
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}
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}
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for( FOOTPRINT* footprint : brd->Footprints() )
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{
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if( typeMask[ PCB_FP_TEXT_T ] )
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{
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if( ( footprint->Reference().GetLayerSet() & aLayers ).any() )
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{
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if( !aFunc( &footprint->Reference() ) )
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return n;
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n++;
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}
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if( ( footprint->Value().GetLayerSet() & aLayers ).any() )
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{
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if( !aFunc( &footprint->Value() ) )
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return n;
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n++;
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}
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}
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if( typeMask[ PCB_PAD_T ] )
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{
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for( PAD* pad : footprint->Pads() )
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{
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// Careful: if a pad has a hole then it pierces all layers
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if( ( pad->GetDrillSizeX() > 0 && pad->GetDrillSizeY() > 0 )
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|| ( pad->GetLayerSet() & aLayers ).any() )
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{
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if( !aFunc( pad ) )
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return n;
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n++;
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}
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}
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}
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for( BOARD_ITEM* dwg : footprint->GraphicalItems() )
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{
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if( (dwg->GetLayerSet() & aLayers).any() )
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{
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if( typeMask[ PCB_DIMENSION_T ] && BaseType( dwg->Type() ) == PCB_DIMENSION_T )
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{
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if( !aFunc( dwg ) )
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return n;
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n++;
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}
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else if( typeMask[ PCB_FP_TEXT_T ] && dwg->Type() == PCB_FP_TEXT_T )
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{
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if( !aFunc( dwg ) )
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return n;
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n++;
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}
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else if( typeMask[ PCB_FP_SHAPE_T ] && dwg->Type() == PCB_FP_SHAPE_T )
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{
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if( !aFunc( dwg ) )
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return n;
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n++;
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}
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}
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}
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if( typeMask[ PCB_FP_ZONE_T ] )
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{
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for( ZONE* zone : footprint->Zones() )
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{
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if( (zone->GetLayerSet() & aLayers).any() )
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{
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if( !aFunc( zone ) )
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return n;
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n++;
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}
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}
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}
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if( typeMask[ PCB_FOOTPRINT_T ] )
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{
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if( !aFunc( footprint ) )
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return n;
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n++;
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}
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}
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return n;
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}
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bool DRC_TEST_PROVIDER::isInvisibleText( const BOARD_ITEM* aItem ) const
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{
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if( const FP_TEXT* text = dyn_cast<const FP_TEXT*>( aItem ) )
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{
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if( !text->IsVisible() )
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return true;
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}
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if( const PCB_TEXT* text = dyn_cast<const PCB_TEXT*>( aItem ) )
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{
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if( !text->IsVisible() )
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return true;
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}
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return false;
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}
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