380 lines
12 KiB
C++
380 lines
12 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <board_design_settings.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_rule_condition.h>
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#include <drc/drc_test_provider.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <drawing_sheet/ds_draw_item.h>
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#include <drawing_sheet/ds_proxy_view_item.h>
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/*
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Miscellaneous tests:
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- DRCE_DISABLED_LAYER_ITEM, ///< item on a disabled layer
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- DRCE_INVALID_OUTLINE, ///< invalid board outline
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- DRCE_UNRESOLVED_VARIABLE,
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- DRCE_ASSERTION_FAILURE ///< user-defined assertions
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*/
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class DRC_TEST_PROVIDER_MISC : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_MISC() :
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m_board( nullptr )
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{
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m_isRuleDriven = false;
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}
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virtual ~DRC_TEST_PROVIDER_MISC()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "miscellaneous" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Misc checks (board outline, missing textvars)" );
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}
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private:
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void testOutline();
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void testDisabledLayers();
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void testTextVars();
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void testAssertions();
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BOARD* m_board;
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};
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void DRC_TEST_PROVIDER_MISC::testOutline()
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{
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SHAPE_POLY_SET dummyOutline;
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bool errorHandled = false;
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OUTLINE_ERROR_HANDLER errorHandler =
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[&]( const wxString& msg, BOARD_ITEM* itemA, BOARD_ITEM* itemB, const VECTOR2I& pt )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_INVALID_OUTLINE );
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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drcItem->SetItems( itemA, itemB );
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reportViolation( drcItem, pt, Edge_Cuts );
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errorHandled = true;
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};
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// Use a really tight chaining epsilon here so that we report errors that might affect
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// other tools (such as STEP export).
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constexpr int chainingEpsilon = Millimeter2iu( 0.02 ) / 100;
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if( !BuildBoardPolygonOutlines( m_board, dummyOutline, m_board->GetDesignSettings().m_MaxError,
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chainingEpsilon, &errorHandler ) )
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{
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if( errorHandled )
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{
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// if there is an invalid outline, then there must be an outline
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}
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else
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_INVALID_OUTLINE );
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m_msg.Printf( _( "(no edges found on Edge.Cuts layer)" ) );
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + m_msg );
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drcItem->SetItems( m_board );
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reportViolation( drcItem, m_board->GetBoundingBox().Centre(), Edge_Cuts );
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}
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}
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}
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void DRC_TEST_PROVIDER_MISC::testDisabledLayers()
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{
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// This is the number of tests between 2 calls to the progress bar
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const int delta = 2000;
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int ii = 0;
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int items = 0;
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auto countItems =
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[&]( BOARD_ITEM* item ) -> bool
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{
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++items;
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return true;
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};
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LSET disabledLayers = m_board->GetEnabledLayers().flip();
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// Perform the test only for copper layers
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disabledLayers &= LSET::AllCuMask();
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auto checkDisabledLayers =
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_DISABLED_LAYER_ITEM ) )
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return false;
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if( !reportProgress( ii++, items, delta ) )
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return false;
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PCB_LAYER_ID badLayer = UNDEFINED_LAYER;
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if( item->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( item );
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if( pad->GetAttribute() == PAD_ATTRIB::SMD
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|| pad->GetAttribute() == PAD_ATTRIB::CONN )
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{
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if( disabledLayers.test( pad->GetPrincipalLayer() ) )
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badLayer = item->GetLayer();
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}
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else
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{
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// Through hole pad is on whatever layers there are.
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}
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}
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else if( item->Type() == PCB_VIA_T )
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{
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PCB_VIA* via = static_cast<PCB_VIA*>( item );
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PCB_LAYER_ID top;
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PCB_LAYER_ID bottom;
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via->LayerPair( &top, &bottom );
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if( disabledLayers.test( top ) )
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badLayer = top;
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else if( disabledLayers.test( bottom ) )
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badLayer = bottom;
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}
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else if( item->Type() == PCB_FP_ZONE_T )
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{
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// Footprint zones just get a top/bottom/inner setting, so they're on
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// whatever inner layers there are.
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}
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else
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{
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LSET badLayers = disabledLayers & item->GetLayerSet();
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if( badLayers.any() )
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badLayer = badLayers.Seq().front();
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}
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if( badLayer != UNDEFINED_LAYER )
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{
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auto drcItem = DRC_ITEM::Create( DRCE_DISABLED_LAYER_ITEM );
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m_msg.Printf( _( "(layer %s)" ), LayerName( badLayer ) );
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + m_msg );
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drcItem->SetItems( item );
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reportViolation( drcItem, item->GetPosition(), UNDEFINED_LAYER );
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}
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return true;
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};
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forEachGeometryItem( s_allBasicItems, LSET::AllLayersMask(), countItems );
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forEachGeometryItem( s_allBasicItems, LSET::AllLayersMask(), checkDisabledLayers );
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}
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void DRC_TEST_PROVIDER_MISC::testAssertions()
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{
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// This is the number of tests between 2 calls to the progress bar
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const int delta = 2000;
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int ii = 0;
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int items = 0;
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auto countItems =
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[&]( BOARD_ITEM* item ) -> bool
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{
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++items;
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return true;
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};
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auto checkAssertions =
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_ASSERTION_FAILURE ) )
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return false;
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if( !reportProgress( ii++, items, delta ) )
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return false;
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m_drcEngine->ProcessAssertions( item,
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[&]( const DRC_CONSTRAINT* c )
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{
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auto drcItem = DRC_ITEM::Create( DRCE_ASSERTION_FAILURE );
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " (" )
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+ c->GetName() + wxS( ")" ) );
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drcItem->SetItems( item );
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reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
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} );
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return true;
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};
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forEachGeometryItem( {}, LSET::AllLayersMask(), countItems );
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forEachGeometryItem( {}, LSET::AllLayersMask(), checkAssertions );
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}
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void DRC_TEST_PROVIDER_MISC::testTextVars()
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{
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// This is the number of tests between 2 calls to the progress bar
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const int delta = 2000;
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int ii = 0;
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int items = 0;
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static const std::vector<KICAD_T> itemTypes = {
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PCB_TEXT_T, PCB_FP_TEXT_T, PCB_TEXTBOX_T, PCB_FP_TEXTBOX_T,
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PCB_DIMENSION_T
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};
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forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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++items;
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return true;
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} );
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forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_UNRESOLVED_VARIABLE ) )
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return false;
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if( !reportProgress( ii++, items, delta ) )
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return false;
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BOARD_ITEM* boardItem = dynamic_cast<BOARD_ITEM*>( item );
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EDA_TEXT* text = dynamic_cast<EDA_TEXT*>( boardItem );
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if( text && text->GetShownText().Matches( wxT( "*${*}*" ) ) )
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{
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std::shared_ptr<DRC_ITEM>drcItem = DRC_ITEM::Create( DRCE_UNRESOLVED_VARIABLE );
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drcItem->SetItems( item );
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reportViolation( drcItem, boardItem->GetPosition(), boardItem->GetLayer() );
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}
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return true;
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} );
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DS_PROXY_VIEW_ITEM* drawingSheet = m_drcEngine->GetDrawingSheet();
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DS_DRAW_ITEM_LIST drawItems;
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if( !drawingSheet || m_drcEngine->IsErrorLimitExceeded( DRCE_UNRESOLVED_VARIABLE ) )
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return;
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drawItems.SetMilsToIUfactor( IU_PER_MILS );
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drawItems.SetPageNumber( wxT( "1" ) );
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drawItems.SetSheetCount( 1 );
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drawItems.SetFileName( wxT( "dummyFilename" ) );
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drawItems.SetSheetName( wxT( "dummySheet" ) );
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drawItems.SetSheetLayer( wxT( "dummyLayer" ) );
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drawItems.SetProject( m_board->GetProject() );
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drawItems.BuildDrawItemsList( drawingSheet->GetPageInfo(), drawingSheet->GetTitleBlock() );
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for( DS_DRAW_ITEM_BASE* item = drawItems.GetFirst(); item; item = drawItems.GetNext() )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_UNRESOLVED_VARIABLE ) )
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break;
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if( m_drcEngine->IsCancelled() )
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return;
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DS_DRAW_ITEM_TEXT* text = dynamic_cast<DS_DRAW_ITEM_TEXT*>( item );
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if( text && text->GetShownText().Matches( wxT( "*${*}*" ) ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_UNRESOLVED_VARIABLE );
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drcItem->SetItems( text );
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reportViolation( drcItem, text->GetPosition(), UNDEFINED_LAYER );
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}
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}
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}
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bool DRC_TEST_PROVIDER_MISC::Run()
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{
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m_board = m_drcEngine->GetBoard();
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_INVALID_OUTLINE ) )
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{
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if( !reportPhase( _( "Checking board outline..." ) ) )
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return false; // DRC cancelled
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testOutline();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_DISABLED_LAYER_ITEM ) )
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{
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if( !reportPhase( _( "Checking disabled layers..." ) ) )
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return false; // DRC cancelled
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testDisabledLayers();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_UNRESOLVED_VARIABLE ) )
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{
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if( !reportPhase( _( "Checking text variables..." ) ) )
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return false; // DRC cancelled
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testTextVars();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_ASSERTION_FAILURE ) )
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{
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if( !reportPhase( _( "Checking assertions..." ) ) )
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return false; // DRC cancelled
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testAssertions();
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}
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MISC> dummy;
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}
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