265 lines
10 KiB
C++
265 lines
10 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2017 CERN
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* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* @author Alejandro García Montoro <alejandro.garciamontoro@gmail.com>
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* @author Maciej Suminski <maciej.suminski@cern.ch>
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* @author Russell Oliver <roliver8143@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 3
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SCH_EAGLE_PLUGIN_H_
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#define _SCH_EAGLE_PLUGIN_H_
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#include <sch_line.h>
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#include <sch_io_mgr.h>
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#include <plugins/eagle/eagle_parser.h>
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#include <lib_item.h>
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#include <geometry/seg.h>
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#include <boost/ptr_container/ptr_map.hpp>
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class EDA_TEXT;
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class KIWAY;
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class LINE_READER;
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class SCH_SCREEN;
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class SCH_SHEET;
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class SCH_BITMAP;
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class SCH_JUNCTION;
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class SCH_NO_CONNECT;
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class SCH_LINE;
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class SCH_BUS_ENTRY_BASE;
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class SCH_TEXT;
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class SCH_GLOBALLABEL;
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class SCH_SYMBOL;
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class SCH_FIELD;
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class PROPERTIES;
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class SCH_EAGLE_PLUGIN_CACHE;
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class LIB_SYMBOL;
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class SYMBOL_LIB;
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class LIB_SHAPE;
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class LIB_FIELD;
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class LIB_RECTANGLE;
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class LIB_POLYLINE;
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class LIB_PIN;
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class LIB_TEXT;
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class wxXmlNode;
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struct EAGLE_LIBRARY
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{
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wxString name;
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boost::ptr_map<wxString, LIB_SYMBOL> KiCadSymbols;
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std::unordered_map<wxString, wxXmlNode*> SymbolNodes;
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std::unordered_map<wxString, int> GateUnit;
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std::unordered_map<wxString, wxString> package;
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};
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typedef boost::ptr_map<wxString, EPART> EPART_LIST;
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/**
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* A #SCH_PLUGIN derivation for loading 6.x+ Eagle schematic files.
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*
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* As with all SCH_PLUGINs there is no UI dependencies i.e. windowing calls allowed.
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*/
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class SCH_EAGLE_PLUGIN : public SCH_PLUGIN
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{
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public:
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SCH_EAGLE_PLUGIN();
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~SCH_EAGLE_PLUGIN();
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const wxString GetName() const override;
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void SetReporter( REPORTER* aReporter ) override { m_reporter = aReporter; }
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void SetProgressReporter( PROGRESS_REPORTER* aReporter ) override
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{
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m_progressReporter = aReporter;
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}
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const wxString GetFileExtension() const override;
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const wxString GetLibraryFileExtension() const override;
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int GetModifyHash() const override;
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SCH_SHEET* Load( const wxString& aFileName, SCHEMATIC* aSchematic,
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SCH_SHEET* aAppendToMe = nullptr,
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const PROPERTIES* aProperties = nullptr ) override;
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bool CheckHeader( const wxString& aFileName ) override;
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private:
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void checkpoint();
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void loadDrawing( wxXmlNode* aDrawingNode );
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void loadLayerDefs( wxXmlNode* aLayers );
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void loadSchematic( wxXmlNode* aSchematicNode );
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void loadSheet( wxXmlNode* aSheetNode, int sheetcount );
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void loadInstance( wxXmlNode* aInstanceNode );
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EAGLE_LIBRARY* loadLibrary( wxXmlNode* aLibraryNode, EAGLE_LIBRARY* aEagleLib );
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void countNets( wxXmlNode* aSchematicNode );
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/// Move any labels on the wire to the new end point of the wire.
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void moveLabels( SCH_LINE* aWire, const VECTOR2I& aNewEndPoint );
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/// This function finds best way to place a bus entry symbol for when an Eagle wire segment
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/// ends on an Eagle bus segment.
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void addBusEntries();
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/// Return the matching layer or return LAYER_NOTES
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SCH_LAYER_ID kiCadLayer( int aEagleLayer );
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std::pair<VECTOR2I, const SEG*> findNearestLinePoint( const VECTOR2I& aPoint,
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const std::vector<SEG>& aLines ) const;
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void loadSegments( wxXmlNode* aSegmentsNode, const wxString& aNetName,
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const wxString& aNetClass );
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SCH_LINE* loadWire( wxXmlNode* aWireNode );
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SCH_TEXT* loadLabel( wxXmlNode* aLabelNode, const wxString& aNetName );
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SCH_JUNCTION* loadJunction( wxXmlNode* aJunction );
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SCH_TEXT* loadPlainText( wxXmlNode* aSchText );
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void loadFrame( wxXmlNode* aFrameNode, std::vector<SCH_LINE*>& aLines );
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bool loadSymbol( wxXmlNode* aSymbolNode, std::unique_ptr<LIB_SYMBOL>& aSymbol,
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EDEVICE* aDevice, int aGateNumber, const wxString& aGateName );
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LIB_SHAPE* loadSymbolCircle( std::unique_ptr<LIB_SYMBOL>& aSymbol, wxXmlNode* aCircleNode,
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int aGateNumber );
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LIB_SHAPE* loadSymbolRectangle( std::unique_ptr<LIB_SYMBOL>& aSymbol, wxXmlNode* aRectNode,
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int aGateNumber );
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LIB_SHAPE* loadSymbolPolyLine( std::unique_ptr<LIB_SYMBOL>& aSymbol,
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wxXmlNode* aPolygonNode, int aGateNumber );
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LIB_ITEM* loadSymbolWire( std::unique_ptr<LIB_SYMBOL>& aSymbol, wxXmlNode* aWireNode,
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int aGateNumber );
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LIB_PIN* loadPin( std::unique_ptr<LIB_SYMBOL>& aSymbol, wxXmlNode*, EPIN* epin,
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int aGateNumber );
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LIB_TEXT* loadSymbolText( std::unique_ptr<LIB_SYMBOL>& aSymbol, wxXmlNode* aLibText,
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int aGateNumber );
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void loadFrame( wxXmlNode* aFrameNode, std::vector<LIB_ITEM*>& aLines );
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void loadTextAttributes( EDA_TEXT* aText, const ETEXT& aAttribs ) const;
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void loadFieldAttributes( LIB_FIELD* aField, const LIB_TEXT* aText ) const;
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///< Move net labels that are detached from any wire to the nearest wire
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void adjustNetLabels();
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/**
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* Translate an Eagle-style bus name into one that is KiCad-compatible.
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*
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* For vector buses such as A[7..0] this has no impact. For group buses, we translate from
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* Eagle-style to KiCad-style.
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*
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* @param aEagleName is the name of the bus from the Eagle schematic
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*/
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wxString translateEagleBusName( const wxString& aEagleName ) const;
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wxString getLibName();
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wxFileName getLibFileName();
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///< Checks if there are other wires or pins at the position of the tested pin
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bool checkConnections( const SCH_SYMBOL* aSymbol, const LIB_PIN* aPin ) const;
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/**
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* Create net labels to emulate implicit connections in Eagle.
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*
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* Each named power input pin creates an implicit connection in Eagle. To emulate this behavior
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* one needs to attach global net labels to the mentioned pins. This is is also expected for the
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* units that are not instantiated in the schematics, therefore such units need to be stored
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* in order to create them at later stage.
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*
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* @param aSymbol is the symbol to process.
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* @param aScreen is the screen where net labels should be added.
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* @param aUpdateSet decides whether the missing units data should be updated.
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*/
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void addImplicitConnections( SCH_SYMBOL* aSymbol, SCH_SCREEN* aScreen, bool aUpdateSet );
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bool netHasPowerDriver( SCH_LINE* aLine, const wxString& aNetName ) const;
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// Describe missing units containing pins creating implicit connections
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// (named power pins in Eagle).
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struct EAGLE_MISSING_CMP
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{
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EAGLE_MISSING_CMP( const SCH_SYMBOL* aSymbol = nullptr )
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: cmp( aSymbol )
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{
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}
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///< Link to the parent symbol
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const SCH_SYMBOL* cmp;
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/* Map of the symbol units: for each unit there is a flag saying
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* whether the unit needs to be instantiated with appropriate net labels to
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* emulate implicit connections as is done in Eagle.
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*/
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std::map<int, bool> units;
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};
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REPORTER* m_reporter; ///< Reporter for warnings/errors
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///< Map references to missing symbol units data
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std::map<wxString, EAGLE_MISSING_CMP> m_missingCmps;
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SCH_SHEET* m_rootSheet; ///< The root sheet of the schematic being loaded
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SCH_SHEET* m_currentSheet; ///< The current sheet of the schematic being loaded
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wxString m_version; ///< Eagle file version.
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wxFileName m_filename;
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wxString m_libName; ///< Library name to save symbols
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SCHEMATIC* m_schematic; ///< Passed to Load(), the schematic object being loaded
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EPART_MAP m_partlist;
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std::map<wxString, EAGLE_LIBRARY> m_eagleLibs;
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SCH_PLUGIN::SCH_PLUGIN_RELEASER m_pi; ///< PI to create KiCad symbol library.
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std::unique_ptr< PROPERTIES > m_properties; ///< Library plugin properties.
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PROGRESS_REPORTER* m_progressReporter; ///< optional; may be nullptr
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unsigned m_doneCount;
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unsigned m_lastProgressCount;
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unsigned m_totalCount; ///< for progress reporting
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std::map<wxString, int> m_netCounts;
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std::map<int, SCH_LAYER_ID> m_layerMap;
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std::map<wxString, wxString> m_powerPorts; ///< map from symbol reference to global
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///< label equivalent
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///< Wire intersection points, used for quick checks whether placing a net label in a particular
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///< place would short two nets.
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std::vector<VECTOR2I> m_wireIntersections;
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///< Wires and labels of a single connection (segment in Eagle nomenclature)
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struct SEG_DESC
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{
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///< Test if a particular label is attached to any of the stored segments
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const SEG* LabelAttached( const SCH_TEXT* aLabel ) const;
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std::vector<SCH_TEXT*> labels;
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std::vector<SEG> segs;
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};
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///< Segments representing wires for intersection checking
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std::vector<SEG_DESC> m_segments;
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///< Nets as defined in the <nets> sections of an Eagle schematic file.
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std::map<wxString, ENET> m_nets;
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///< Positions of pins and wire endings mapped to its parent
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std::map<VECTOR2I, std::set<const EDA_ITEM*>> m_connPoints;
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};
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#endif // _SCH_EAGLE_PLUGIN_H_
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