114 lines
4.3 KiB
C++
114 lines
4.3 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019 Thomas Pointhuber <thomas.pointhuber@gmx.at>
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* Copyright (C) 2020-2023 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @brief Pcbnew PLUGIN for Altium *.PcbDoc format.
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*/
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#include <wx/string.h>
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#include <pcb_io_altium_circuit_maker.h>
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#include <pcb_io_altium_designer.h>
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#include <altium_pcb.h>
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#include <io/altium/altium_binary_parser.h>
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#include <pcb_io/pcb_io.h>
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#include <board.h>
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#include <compoundfilereader.h>
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#include <utf.h>
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PCB_IO_ALTIUM_CIRCUIT_MAKER::PCB_IO_ALTIUM_CIRCUIT_MAKER() : PCB_IO( wxS( "Altium Circuit Maker" ) )
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{
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RegisterLayerMappingCallback( PCB_IO_ALTIUM_DESIGNER::DefaultLayerMappingCallback );
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}
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PCB_IO_ALTIUM_CIRCUIT_MAKER::~PCB_IO_ALTIUM_CIRCUIT_MAKER()
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{
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}
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bool PCB_IO_ALTIUM_CIRCUIT_MAKER::CanReadBoard( const wxString& aFileName ) const
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{
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if( !PCB_IO::CanReadBoard( aFileName ) )
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return false;
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return PCB_IO_ALTIUM_DESIGNER::checkFileHeader( aFileName );
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}
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BOARD* PCB_IO_ALTIUM_CIRCUIT_MAKER::LoadBoard( const wxString& aFileName, BOARD* aAppendToMe,
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const STRING_UTF8_MAP* aProperties,
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PROJECT* aProject )
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{
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m_props = aProperties;
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m_board = aAppendToMe ? aAppendToMe : new BOARD();
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// Give the filename to the board if it's new
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if( !aAppendToMe )
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m_board->SetFileName( aFileName );
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// clang-format off
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const std::map<ALTIUM_PCB_DIR, std::string> mapping = {
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{ ALTIUM_PCB_DIR::FILE_HEADER, "FileHeader" },
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{ ALTIUM_PCB_DIR::ARCS6, "1CEEB63FB33847F8AFC4485F64735E" },
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{ ALTIUM_PCB_DIR::BOARD6, "96B09F5C6CEE434FBCE0DEB3E88E70" },
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{ ALTIUM_PCB_DIR::BOARDREGIONS, "E3A544335C30403A991912052C936F" },
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{ ALTIUM_PCB_DIR::CLASSES6, "4F71DD45B09143988210841EA1C28D" },
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{ ALTIUM_PCB_DIR::COMPONENTS6, "F9D060ACC7DD4A85BC73CB785BAC81" },
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{ ALTIUM_PCB_DIR::COMPONENTBODIES6, "44D9487C98CE4F0EB46AB6E9CDAF40" }, // or: A0DB41FBCB0D49CE8C32A271AA7EF5 ?
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{ ALTIUM_PCB_DIR::DIMENSIONS6, "068B9422DBB241258BA2DE9A6BA1A6" },
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{ ALTIUM_PCB_DIR::FILLS6, "6FFE038462A940E9B422EFC8F5D85E" },
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{ ALTIUM_PCB_DIR::MODELS, "0DB009C021D946C88F1B3A32DAE94B" },
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{ ALTIUM_PCB_DIR::NETS6, "35D7CF51BB9B4875B3A138B32D80DC" },
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{ ALTIUM_PCB_DIR::PADS6, "4F501041A9BC4A06BDBDAB67D3820E" },
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{ ALTIUM_PCB_DIR::POLYGONS6, "A1931C8B0B084A61AA45146575FDD3" },
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{ ALTIUM_PCB_DIR::REGIONS6, "F513A5885418472886D3EF18A09E46" },
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{ ALTIUM_PCB_DIR::RULES6, "C27718A40C94421388FAE5BD7785D7" },
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{ ALTIUM_PCB_DIR::SHAPEBASEDREGIONS6,"BDAA2C70289849078C8EBEEC7F0848" },
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{ ALTIUM_PCB_DIR::TEXTS6, "A34BC67C2A5F408D8F377378C5C5E2" },
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{ ALTIUM_PCB_DIR::TRACKS6, "412A754DBB864645BF01CD6A80C358" },
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{ ALTIUM_PCB_DIR::VIAS6, "C87A685A0EFA4A90BEEFD666198B56" },
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{ ALTIUM_PCB_DIR::WIDESTRINGS6, "C1C6540EA23C48D3BF8F9A4ABB9D6D" }
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};
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// clang-format on
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ALTIUM_COMPOUND_FILE altiumPcbFile( aFileName );
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try
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{
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// Parse File
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ALTIUM_PCB pcb( m_board, m_progressReporter, m_layer_mapping_handler, m_reporter );
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pcb.Parse( altiumPcbFile, mapping );
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}
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catch( CFB::CFBException& exception )
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{
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THROW_IO_ERROR( exception.what() );
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}
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return m_board;
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}
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