114 lines
4.3 KiB
C++
114 lines
4.3 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019 Thomas Pointhuber <thomas.pointhuber@gmx.at>
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* Copyright (C) 2020-2023 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @brief Pcbnew PLUGIN for Altium *.PcbDoc format.
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*/
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#include <wx/string.h>
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#include <pcb_io_altium_circuit_studio.h>
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#include <pcb_io_altium_designer.h>
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#include <altium_pcb.h>
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#include <io/altium/altium_binary_parser.h>
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#include <pcb_io/pcb_io.h>
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#include <board.h>
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#include <compoundfilereader.h>
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#include <utf.h>
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PCB_IO_ALTIUM_CIRCUIT_STUDIO::PCB_IO_ALTIUM_CIRCUIT_STUDIO() : PCB_IO( wxS( "Altium Circuit Studio" ) )
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{
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RegisterLayerMappingCallback( PCB_IO_ALTIUM_DESIGNER::DefaultLayerMappingCallback );
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}
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PCB_IO_ALTIUM_CIRCUIT_STUDIO::~PCB_IO_ALTIUM_CIRCUIT_STUDIO()
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{
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}
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bool PCB_IO_ALTIUM_CIRCUIT_STUDIO::CanReadBoard( const wxString& aFileName ) const
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{
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if( !PCB_IO::CanReadBoard( aFileName ) )
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return false;
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return PCB_IO_ALTIUM_DESIGNER::checkFileHeader( aFileName );
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}
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BOARD* PCB_IO_ALTIUM_CIRCUIT_STUDIO::LoadBoard( const wxString& aFileName, BOARD* aAppendToMe,
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const STRING_UTF8_MAP* aProperties,
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PROJECT* aProject )
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{
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m_props = aProperties;
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m_board = aAppendToMe ? aAppendToMe : new BOARD();
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// Give the filename to the board if it's new
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if( !aAppendToMe )
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m_board->SetFileName( aFileName );
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// clang-format off
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const std::map<ALTIUM_PCB_DIR, std::string> mapping = {
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{ ALTIUM_PCB_DIR::FILE_HEADER, "FileHeader" },
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{ ALTIUM_PCB_DIR::ARCS6, "00C595EB90524FFC8C3BD9670020A2" },
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{ ALTIUM_PCB_DIR::BOARD6, "88857D7F1DF64F7BBB61848C965636" },
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{ ALTIUM_PCB_DIR::BOARDREGIONS, "8957CF30F167408D9D263D23FE7C89" },
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{ ALTIUM_PCB_DIR::CLASSES6, "847EFBF87A5149B1AA326A52AD6357" },
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{ ALTIUM_PCB_DIR::COMPONENTS6, "465416896A15486999A39C643935D2" },
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{ ALTIUM_PCB_DIR::COMPONENTBODIES6, "1849D9B5512D452A93EABF4E40B122" }, // or B6AD30D75241498BA2536EBF001752 ?
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{ ALTIUM_PCB_DIR::DIMENSIONS6, "16C81DBC13C447FF8B42A426677F3C" },
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{ ALTIUM_PCB_DIR::FILLS6, "4E83BDC3253747F08E9006D7F57020" },
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{ ALTIUM_PCB_DIR::MODELS, "C0F7599ECC6A4D648DF5BB557679AF" },
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{ ALTIUM_PCB_DIR::NETS6, "D95A0DA2FE9047779A5194C127F30B" },
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{ ALTIUM_PCB_DIR::PADS6, "47D69BC5107A4B8DB8DAA23E39C238" },
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{ ALTIUM_PCB_DIR::POLYGONS6, "D7038392280E4E229B9D9B5426B295" },
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{ ALTIUM_PCB_DIR::REGIONS6, "FFDDC21382BB42FE8A7D0C328D272C" },
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{ ALTIUM_PCB_DIR::RULES6, "48B2FA96DB7546818752B34373D6C6" },
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{ ALTIUM_PCB_DIR::SHAPEBASEDREGIONS6, "D5F54B536E124FB89E2D51B1121508" },
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{ ALTIUM_PCB_DIR::TEXTS6, "349ABBB211DB4F5B8AE41B1B49555A" },
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{ ALTIUM_PCB_DIR::TRACKS6, "530C20C225354B858B2578CAB8C08D" },
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{ ALTIUM_PCB_DIR::VIAS6, "CA5F5989BCDB404DA70A9D1D3D5758" },
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{ ALTIUM_PCB_DIR::WIDESTRINGS6, "87FBF0C5BC194B909FF42199450A76" }
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};
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// clang-format on
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ALTIUM_COMPOUND_FILE altiumPcbFile( aFileName );
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try
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{
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// Parse File
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ALTIUM_PCB pcb( m_board, m_progressReporter, m_layer_mapping_handler, m_reporter );
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pcb.Parse( altiumPcbFile, mapping );
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}
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catch( CFB::CFBException& exception )
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{
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THROW_IO_ERROR( exception.what() );
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}
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return m_board;
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}
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