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@ -47,39 +47,40 @@ module tt_um_xeniarose_sha256 (
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reg [7 : 0] io_out;
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assign uio_out = io_out;
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reg [ 31 : 0 ] A_reg;
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reg [ 31 : 0 ] B_reg;
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reg [ 31 : 0 ] C_reg;
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reg [ 31 : 0 ] D_reg;
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reg [ 31 : 0 ] E_reg;
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reg [ 31 : 0 ] F_reg;
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reg [ 31 : 0 ] G_reg;
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reg [ 31 : 0 ] H_reg;
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reg [ 31 : 0 ] register_file [ 9 : 0 ];
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reg [ 31 : 0 ] W_reg;
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reg [ 31 : 0 ] K_reg;
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`define A_reg register_file[0]
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`define B_reg register_file[1]
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`define C_reg register_file[2]
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`define D_reg register_file[3]
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`define E_reg register_file[4]
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`define F_reg register_file[5]
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`define G_reg register_file[6]
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`define H_reg register_file[7]
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`define W_reg register_file[8]
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`define K_reg register_file[9]
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wire [ 31 : 0 ] s1 =
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{E_reg[5:0],E_reg[31:6]} ^ {E_reg[10:0],E_reg[31:11]} ^ {E_reg[24:0],E_reg[31:25]};
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wire [ 31 : 0 ] ch = (E_reg & F_reg) ^ ((~E_reg) & G_reg);
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wire [ 31 : 0 ] temp1 = H_reg + s1 + ch + K_reg + W_reg;
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{`E_reg[5:0],`E_reg[31:6]} ^ {`E_reg[10:0],`E_reg[31:11]} ^ {`E_reg[24:0],`E_reg[31:25]};
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wire [ 31 : 0 ] ch = (`E_reg & `F_reg) ^ ((~`E_reg) & `G_reg);
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wire [ 31 : 0 ] temp1 = `H_reg + s1 + ch + `K_reg + `W_reg;
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wire [ 31 : 0 ] s0 =
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{A_reg[1:0],A_reg[31:2]} ^ {A_reg[12:0],A_reg[31:13]} ^ {A_reg[21:0],A_reg[31:22]};
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wire [ 31 : 0 ] maj = (A_reg & B_reg) ^ (A_reg & C_reg) ^ (B_reg & C_reg);
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{`A_reg[1:0],`A_reg[31:2]} ^ {`A_reg[12:0],`A_reg[31:13]} ^ {`A_reg[21:0],`A_reg[31:22]};
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wire [ 31 : 0 ] maj = (`A_reg & `B_reg) ^ (`A_reg & `C_reg) ^ (`B_reg & `C_reg);
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wire [ 31 : 0 ] temp2 = s0 + maj;
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always @(posedge clk or negedge rst_n) begin : io_proc
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if (!rst_n) begin
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A_reg <= 32'h0;
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B_reg <= 32'h0;
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C_reg <= 32'h0;
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D_reg <= 32'h0;
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E_reg <= 32'h0;
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F_reg <= 32'h0;
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G_reg <= 32'h0;
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H_reg <= 32'h0;
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W_reg <= 32'h0;
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K_reg <= 32'h0;
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register_file[0] <= 32'h0;
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register_file[1] <= 32'h0;
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register_file[2] <= 32'h0;
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register_file[3] <= 32'h0;
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register_file[4] <= 32'h0;
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register_file[5] <= 32'h0;
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register_file[6] <= 32'h0;
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register_file[7] <= 32'h0;
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register_file[8] <= 32'h0;
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register_file[9] <= 32'h0;
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io_out <= 8'h0;
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io_ready <= 0;
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@ -89,120 +90,38 @@ module tt_um_xeniarose_sha256 (
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if (io_clk) begin
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if (!io_we) begin
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case (io_addr)
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0: begin
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A_reg <= temp1 + temp2;
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B_reg <= A_reg;
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C_reg <= B_reg;
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D_reg <= C_reg;
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E_reg <= D_reg + temp1;
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F_reg <= E_reg;
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G_reg <= F_reg;
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H_reg <= G_reg;
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63: begin
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`A_reg <= temp1 + temp2;
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`B_reg <= `A_reg;
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`C_reg <= `B_reg;
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`D_reg <= `C_reg;
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`E_reg <= `D_reg + temp1;
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`F_reg <= `E_reg;
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`G_reg <= `F_reg;
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`H_reg <= `G_reg;
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end
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4: begin W_reg[ 7 : 0] <= uio_in; end
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5: begin W_reg[15 : 8] <= uio_in; end
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6: begin W_reg[23 : 16] <= uio_in; end
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7: begin W_reg[31 : 24] <= uio_in; end
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8: begin K_reg[ 7 : 0] <= uio_in; end
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9: begin K_reg[15 : 8] <= uio_in; end
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10: begin K_reg[23 : 16] <= uio_in; end
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11: begin K_reg[31 : 24] <= uio_in; end
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32: begin A_reg[ 7 : 0] <= uio_in; end
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33: begin A_reg[15 : 8] <= uio_in; end
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34: begin A_reg[23 : 16] <= uio_in; end
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35: begin A_reg[31 : 24] <= uio_in; end
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36: begin B_reg[ 7 : 0] <= uio_in; end
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37: begin B_reg[15 : 8] <= uio_in; end
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38: begin B_reg[23 : 16] <= uio_in; end
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39: begin B_reg[31 : 24] <= uio_in; end
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40: begin C_reg[ 7 : 0] <= uio_in; end
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41: begin C_reg[15 : 8] <= uio_in; end
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42: begin C_reg[23 : 16] <= uio_in; end
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43: begin C_reg[31 : 24] <= uio_in; end
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44: begin D_reg[ 7 : 0] <= uio_in; end
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45: begin D_reg[15 : 8] <= uio_in; end
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46: begin D_reg[23 : 16] <= uio_in; end
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47: begin D_reg[31 : 24] <= uio_in; end
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48: begin E_reg[ 7 : 0] <= uio_in; end
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49: begin E_reg[15 : 8] <= uio_in; end
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50: begin E_reg[23 : 16] <= uio_in; end
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51: begin E_reg[31 : 24] <= uio_in; end
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52: begin F_reg[ 7 : 0] <= uio_in; end
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53: begin F_reg[15 : 8] <= uio_in; end
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54: begin F_reg[23 : 16] <= uio_in; end
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55: begin F_reg[31 : 24] <= uio_in; end
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56: begin G_reg[ 7 : 0] <= uio_in; end
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57: begin G_reg[15 : 8] <= uio_in; end
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58: begin G_reg[23 : 16] <= uio_in; end
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59: begin G_reg[31 : 24] <= uio_in; end
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60: begin H_reg[ 7 : 0] <= uio_in; end
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61: begin H_reg[15 : 8] <= uio_in; end
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62: begin H_reg[23 : 16] <= uio_in; end
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63: begin H_reg[31 : 24] <= uio_in; end
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default: begin
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case (io_addr[1:0])
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2'h0: begin register_file[io_addr[5:2]][7 : 0] <= uio_in; end
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2'h1: begin register_file[io_addr[5:2]][15 : 8] <= uio_in; end
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2'h2: begin register_file[io_addr[5:2]][23 : 16] <= uio_in; end
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2'h3: begin register_file[io_addr[5:2]][31 : 24] <= uio_in; end
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endcase
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end
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endcase
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end else begin
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case (io_addr)
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0: begin io_out[7 : 0] <= 8'h0; end
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63: begin io_out <= 8'h0; end
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4: begin io_out <= W_reg[ 7 : 0]; end
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5: begin io_out <= W_reg[15 : 8]; end
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6: begin io_out <= W_reg[23 : 16]; end
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7: begin io_out <= W_reg[31 : 24]; end
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8: begin io_out <= K_reg[ 7 : 0]; end
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9: begin io_out <= K_reg[15 : 8]; end
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10: begin io_out <= K_reg[23 : 16]; end
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11: begin io_out <= K_reg[31 : 24]; end
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32: begin io_out <= A_reg[ 7 : 0]; end
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33: begin io_out <= A_reg[15 : 8]; end
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34: begin io_out <= A_reg[23 : 16]; end
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35: begin io_out <= A_reg[31 : 24]; end
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36: begin io_out <= B_reg[ 7 : 0]; end
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37: begin io_out <= B_reg[15 : 8]; end
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38: begin io_out <= B_reg[23 : 16]; end
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39: begin io_out <= B_reg[31 : 24]; end
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40: begin io_out <= C_reg[ 7 : 0]; end
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41: begin io_out <= C_reg[15 : 8]; end
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42: begin io_out <= C_reg[23 : 16]; end
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43: begin io_out <= C_reg[31 : 24]; end
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44: begin io_out <= D_reg[ 7 : 0]; end
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45: begin io_out <= D_reg[15 : 8]; end
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46: begin io_out <= D_reg[23 : 16]; end
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47: begin io_out <= D_reg[31 : 24]; end
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48: begin io_out <= E_reg[ 7 : 0]; end
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49: begin io_out <= E_reg[15 : 8]; end
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50: begin io_out <= E_reg[23 : 16]; end
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51: begin io_out <= E_reg[31 : 24]; end
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52: begin io_out <= F_reg[ 7 : 0]; end
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53: begin io_out <= F_reg[15 : 8]; end
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54: begin io_out <= F_reg[23 : 16]; end
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55: begin io_out <= F_reg[31 : 24]; end
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56: begin io_out <= G_reg[ 7 : 0]; end
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57: begin io_out <= G_reg[15 : 8]; end
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58: begin io_out <= G_reg[23 : 16]; end
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59: begin io_out <= G_reg[31 : 24]; end
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60: begin io_out <= H_reg[ 7 : 0]; end
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61: begin io_out <= H_reg[15 : 8]; end
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62: begin io_out <= H_reg[23 : 16]; end
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63: begin io_out <= H_reg[31 : 24]; end
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default: begin
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case (io_addr[1:0])
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2'h0: begin io_out <= register_file[io_addr[5:2]][7 : 0]; end
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2'h1: begin io_out <= register_file[io_addr[5:2]][15 : 8]; end
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2'h2: begin io_out <= register_file[io_addr[5:2]][23 : 16]; end
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2'h3: begin io_out <= register_file[io_addr[5:2]][31 : 24]; end
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endcase
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end
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endcase
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end
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end
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