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xenia/test
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@ -9,14 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
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## How it works
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This is a minimal SHA-256 hash core implemented in a single-cycle-round architecture. TODO: expand
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on this
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Explain how your project works
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## How to test
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TODO: write instructions
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Explain how to use your project
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## External hardware
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No external hardware is needed besides some method of interacting with the bus to transfer commands
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and data.
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List external hardware used in your project (e.g. PMOD, LED display, etc), if any
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@ -8,7 +8,7 @@ project:
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clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)
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# How many tiles your design occupies? A single tile is about 167x108 uM.
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tiles: "2x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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# Your top module name must start with "tt_um_". Make it unique by including your github username:
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top_module: "tt_um_xeniarose_sha256"
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@ -12,7 +12,7 @@
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# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
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# Users have reported that values up to 0.8 worked well for them.
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set ::env(PL_TARGET_DENSITY) 0.8
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set ::env(PL_TARGET_DENSITY) 0.6
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# CLOCK_PERIOD - Increase this in case you are getting setup time violations.
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# The value is in nanoseconds, so 20ns == 50MHz.
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2024 xenia dragon
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* Copyright (c) 2024 xenia dragon
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* SPDX-License-Identifier: Apache-2.0
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*
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* [usagi holding floppy disk.png] i'll just warn you right now, i don't know how to use a computer
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229
test/test.py
229
test/test.py
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@ -1,96 +1,13 @@
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# SPDX-FileCopyrightText: Copyright (c) 2024 xenia dragon
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# SPDX-License-Identifier: Apache-2.0
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import hashlib
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import struct
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# SPDX-FileCopyrightText: © 2024 Tiny Tapeout
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# SPDX-License-Identifier: MIT
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import ClockCycles
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IO_RWSEL = 0b0100_0000
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IO_CLK = 0b1000_0000
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MODE_READ = 1
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MODE_WRITE = 2
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class TestMeta:
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def __init__(self):
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self.mode = None
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async def io_write(dut, meta: TestMeta, addr: int, word: int) -> None:
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assert addr & 0b11 == 0
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if meta.mode != MODE_WRITE:
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dut.ui_in.value = 0
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await ClockCycles(dut.clk, 1)
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meta.mode = MODE_WRITE
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assert (dut.uo_out.value >> 1) & 1 == 0
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assert dut.uio_oe.value == 0x00
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await ClockCycles(dut.clk, 1)
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for i in range(4):
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# dut._log.info("writing %s=%s",
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# f"{addr | i:02x}",
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# f"{(word >> (i*8)) & 0xFF:08b}")
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dut.uio_in.value = (word >> (i*8)) & 0xFF
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dut.ui_in.value = IO_CLK | addr | i
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await ClockCycles(dut.clk, 1)
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dut.uio_in.value = (word >> (i*8)) & 0xFF
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dut.ui_in.value = addr | i
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await ClockCycles(dut.clk, 1)
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async def io_read(dut, meta: TestMeta, addr: int) -> int:
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assert addr & 0b11 == 0
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if meta.mode != MODE_READ:
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dut.ui_in.value = IO_RWSEL
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await ClockCycles(dut.clk, 1)
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meta.mode = MODE_READ
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assert (dut.uo_out.value >> 1) & 1 == 1
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assert dut.uio_oe.value == 0xff
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await ClockCycles(dut.clk, 1)
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word = 0
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for i in range(4):
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dut.ui_in.value = IO_CLK | IO_RWSEL | addr | i
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await ClockCycles(dut.clk, 1)
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dut.ui_in.value = IO_RWSEL | addr | i
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await ClockCycles(dut.clk, 1)
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word |= (dut.uio_out.value & 0xFF) << (i*8)
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# dut._log.info("reading %s=%s",
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# f"{addr | i:02x}",
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# dut.uio_out.value)
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return word
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async def io_trigger(dut, meta: TestMeta) -> None:
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if meta.mode != MODE_WRITE:
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dut.ui_in.value = 0
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await ClockCycles(dut.clk, 1)
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meta.mode = MODE_WRITE
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assert (dut.uo_out.value >> 1) & 1 == 0
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assert dut.uio_oe.value == 0x00
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await ClockCycles(dut.clk, 1)
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dut.uio_in.value = 0
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dut.ui_in.value = IO_CLK | 63
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await ClockCycles(dut.clk, 1)
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dut.uio_in.value = 0
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dut.ui_in.value = 63
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await ClockCycles(dut.clk, 1)
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async def test_init(dut):
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meta = TestMeta()
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@cocotb.test()
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async def test_project(dut):
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dut._log.info("Start")
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# Set the clock period to 10 us (100 KHz)
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@ -106,134 +23,18 @@ async def test_init(dut):
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await ClockCycles(dut.clk, 10)
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dut.rst_n.value = 1
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return meta
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dut._log.info("Test project behavior")
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# Set the input values you want to test
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dut.ui_in.value = 20
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dut.uio_in.value = 30
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@cocotb.test()
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async def test_registers(dut):
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meta = await test_init(dut)
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dut._log.info("Test registers")
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# Wait for one clock cycle to see the output values
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await ClockCycles(dut.clk, 1)
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for addr in range(0, 40, 4):
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dut._log.info("Test register %s", addr)
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for val in [0x1312621, 0, 0xffffffff, 0x13371337, 0x55aa9966]:
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await io_write(dut, meta, addr, val)
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rval = await io_read(dut, meta, addr)
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assert val == rval
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# The following assersion is just an example of how to check the output values.
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# Change it to match the actual expected output of your module:
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assert dut.uo_out.value == 50
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K = [0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
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0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
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0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
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0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
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0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
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0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
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0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
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0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
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0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
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0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
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0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
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0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
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0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
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0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
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0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
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0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2]
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H = [0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
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0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19]
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def _rotr(x, y):
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return ((x >> y) | (x << (32 - y))) & 0xFFFFFFFF
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def _maj(x, y, z):
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return (x & y) ^ (x & z) ^ (y & z)
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def _ch(x, y, z):
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return (x & y) ^ ((~x) & z)
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@cocotb.test()
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async def test_sha_round(dut):
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meta = await test_init(dut)
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dut._log.info("Test SHA-2 compression cycle")
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for w in [0x1312621, 0, 0xffffffff, 0x13371337, 0x55aa9966]:
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for i in range(8):
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await io_write(dut, meta, i*4, H[i])
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await io_write(dut, meta, 32, w)
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await io_write(dut, meta, 36, K[0])
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await io_trigger(dut, meta)
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a, b, c, d, e, f, g, h = H
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s0 = _rotr(a, 2) ^ _rotr(a, 13) ^ _rotr(a, 22)
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t2 = s0 + _maj(a, b, c)
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s1 = _rotr(e, 6) ^ _rotr(e, 11) ^ _rotr(e, 25)
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t1 = h + s1 + _ch(e, f, g) + K[0] + w
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h = g
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g = f
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f = e
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e = (d + t1) & 0xFFFFFFFF
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d = c
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c = b
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b = a
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a = (t1 + t2) & 0xFFFFFFFF
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expected = [a, b, c, d, e, f, g, h]
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for i in range(8):
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actual = await io_read(dut, meta, i*4)
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assert actual == expected[i]
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async def test_one_sha_full(dut, meta, message: bytes) -> None:
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reference_hash = hashlib.sha256(message).digest()
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mdi = len(message) & 0x3F
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length = struct.pack('!Q', len(message) << 3)
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if mdi < 56:
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padlen = 55 - mdi
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else:
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padlen = 119 - mdi
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message = message + b'\x80' + (b'\x00' * padlen) + length
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assert len(message) % 64 == 0
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h = list(H)
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for chunk_idx in range(0, len(message), 64):
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chunk = message[chunk_idx:chunk_idx+64]
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for i in range(8):
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await io_write(dut, meta, i*4, h[i])
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w = [0] * 64
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w[0:16] = struct.unpack('!16L', chunk)
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for i in range(16, 64):
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s0 = _rotr(w[i-15], 7) ^ _rotr(w[i-15], 18) ^ (w[i-15] >> 3)
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s1 = _rotr(w[i-2], 17) ^ _rotr(w[i-2], 19) ^ (w[i-2] >> 10)
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w[i] = (w[i-16] + s0 + w[i-7] + s1) & 0xFFFFFFFF
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for i in range(64):
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await io_write(dut, meta, 32, w[i])
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await io_write(dut, meta, 36, K[i])
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await io_trigger(dut, meta)
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for i in range(8):
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h[i] = (h[i] + (await io_read(dut, meta, i*4))) & 0xFFFFFFFF
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result = struct.pack("!IIIIIIII", *h)
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assert result == reference_hash
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@cocotb.test()
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async def test_sha_full(dut):
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meta = await test_init(dut)
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dut._log.info("Test SHA-2 full hash")
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await test_one_sha_full(dut, meta, b"")
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await test_one_sha_full(dut, meta, b"message digest")
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await test_one_sha_full(dut, meta, b"trans rights")
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await test_one_sha_full(dut, meta, b"abababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababababab")
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# Keep testing the module by changing the input values, waiting for
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# one or more clock cycles, and asserting the expected output values.
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