54 lines
1.8 KiB
YAML
54 lines
1.8 KiB
YAML
# Tiny Tapeout project information
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project:
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title: "tiny sha256" # Project title
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author: "xenia dragon" # Your name
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discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
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description: "a minimal single-cycle-round sha256 core intended to fit in one tile" # One line description of what your project does
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language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
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clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)
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# How many tiles your design occupies? A single tile is about 167x108 uM.
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tiles: "2x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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# Your top module name must start with "tt_um_". Make it unique by including your github username:
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top_module: "tt_um_xeniarose_sha256"
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# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
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source_files:
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- "project.v"
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
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pinout:
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# Inputs
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ui[0]: "addressed register bit 0"
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ui[1]: "addressed register bit 1"
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ui[2]: "addressed register bit 2"
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ui[3]: "addressed register bit 3"
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ui[4]: "addressed register bit 4"
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ui[5]: "addressed register bit 5"
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ui[6]: "IO read/write select"
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ui[7]: "IO clock"
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# Outputs
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uo[0]: "ready"
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uo[1]: "IO read/write selected"
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uo[2]: "todo0"
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uo[3]: "todo1"
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uo[4]: "todo2"
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uo[5]: "todo3"
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uo[6]: "todo4"
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uo[7]: "todo5"
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# Bidirectional pins
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uio[0]: "data bit 0"
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uio[1]: "data bit 1"
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uio[2]: "data bit 2"
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uio[3]: "data bit 3"
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uio[4]: "data bit 4"
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uio[5]: "data bit 5"
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uio[6]: "data bit 6"
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uio[7]: "data bit 7"
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# Do not change!
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yaml_version: 6
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