133 lines
4.2 KiB
Verilog
133 lines
4.2 KiB
Verilog
/*
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* SPDX-FileCopyrightText: Copyright (c) 2024 xenia dragon
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* SPDX-License-Identifier: Apache-2.0
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*
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* [usagi holding floppy disk.png] i'll just warn you right now, i don't know how to use a computer
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*
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* this is quite literally the first time i've written verilog. i have some VHDL experience but if
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* this code is spaghetti, i'm sorry ;____;
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*/
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`default_nettype none
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module tt_um_xeniarose_sha256 (
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input wire [7:0] ui_in, // Dedicated inputs
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output wire [7:0] uo_out, // Dedicated outputs
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input wire [7:0] uio_in, // IOs: Input path
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output wire [7:0] uio_out, // IOs: Output path
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output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
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input wire ena, // always 1 when the design is powered, so you can ignore it
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input wire clk, // clock
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input wire rst_n // reset_n - low to reset
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);
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// All output pins must be assigned. If not used, assign to 0.
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// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
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// assign uio_out = 0;
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// assign uio_oe = 0;
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wire [ 5 : 0 ] io_addr = ui_in[5 : 0];
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wire io_we = ui_in[6];
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wire io_clk = ui_in[7];
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reg io_ready;
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assign uo_out[0] = io_ready;
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assign uo_out[1] = io_we;
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assign uo_out[7 : 2] = 6'h0;
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assign uio_oe[0] = io_we;
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assign uio_oe[1] = io_we;
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assign uio_oe[2] = io_we;
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assign uio_oe[3] = io_we;
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assign uio_oe[4] = io_we;
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assign uio_oe[5] = io_we;
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assign uio_oe[6] = io_we;
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assign uio_oe[7] = io_we;
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reg [7 : 0] io_out;
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assign uio_out = io_out;
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reg [ 31 : 0 ] register_file [ 9 : 0 ];
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`define A_reg register_file[0]
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`define B_reg register_file[1]
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`define C_reg register_file[2]
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`define D_reg register_file[3]
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`define E_reg register_file[4]
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`define F_reg register_file[5]
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`define G_reg register_file[6]
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`define H_reg register_file[7]
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`define W_reg register_file[8]
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`define K_reg register_file[9]
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wire [ 31 : 0 ] s1 =
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{`E_reg[5:0],`E_reg[31:6]} ^ {`E_reg[10:0],`E_reg[31:11]} ^ {`E_reg[24:0],`E_reg[31:25]};
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wire [ 31 : 0 ] ch = (`E_reg & `F_reg) ^ ((~`E_reg) & `G_reg);
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wire [ 31 : 0 ] temp1 = `H_reg + s1 + ch + `K_reg + `W_reg;
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wire [ 31 : 0 ] s0 =
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{`A_reg[1:0],`A_reg[31:2]} ^ {`A_reg[12:0],`A_reg[31:13]} ^ {`A_reg[21:0],`A_reg[31:22]};
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wire [ 31 : 0 ] maj = (`A_reg & `B_reg) ^ (`A_reg & `C_reg) ^ (`B_reg & `C_reg);
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wire [ 31 : 0 ] temp2 = s0 + maj;
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always @(posedge clk or negedge rst_n) begin : io_proc
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if (!rst_n) begin
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register_file[0] <= 32'h0;
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register_file[1] <= 32'h0;
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register_file[2] <= 32'h0;
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register_file[3] <= 32'h0;
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register_file[4] <= 32'h0;
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register_file[5] <= 32'h0;
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register_file[6] <= 32'h0;
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register_file[7] <= 32'h0;
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register_file[8] <= 32'h0;
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register_file[9] <= 32'h0;
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io_out <= 8'h0;
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io_ready <= 0;
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end else begin
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io_ready <= 1;
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if (io_clk) begin
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if (!io_we) begin
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case (io_addr)
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63: begin
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`A_reg <= temp1 + temp2;
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`B_reg <= `A_reg;
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`C_reg <= `B_reg;
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`D_reg <= `C_reg;
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`E_reg <= `D_reg + temp1;
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`F_reg <= `E_reg;
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`G_reg <= `F_reg;
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`H_reg <= `G_reg;
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end
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default: begin
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case (io_addr[1:0])
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2'h0: begin register_file[io_addr[5:2]][7 : 0] <= uio_in; end
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2'h1: begin register_file[io_addr[5:2]][15 : 8] <= uio_in; end
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2'h2: begin register_file[io_addr[5:2]][23 : 16] <= uio_in; end
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2'h3: begin register_file[io_addr[5:2]][31 : 24] <= uio_in; end
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endcase
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end
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endcase
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end else begin
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case (io_addr)
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63: begin io_out <= 8'h0; end
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default: begin
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case (io_addr[1:0])
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2'h0: begin io_out <= register_file[io_addr[5:2]][7 : 0]; end
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2'h1: begin io_out <= register_file[io_addr[5:2]][15 : 8]; end
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2'h2: begin io_out <= register_file[io_addr[5:2]][23 : 16]; end
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2'h3: begin io_out <= register_file[io_addr[5:2]][31 : 24]; end
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endcase
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end
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endcase
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end
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end
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end
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end // rst_proc
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endmodule
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