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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
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How to Apply These Terms to Your New Programs
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# xilinx 7-series tools
WARNING: very poor code quality. expect that you'll probably have to make changes to fit your needs
- xilbitstream.py - a script that prints the contents of 7-series bitstreams and saves files for
any configuration frames found inside. supports either endian, with or without the xilinx
header. nominally does not crash on encrypted bitstreams (!!), but of course it can't really
make any sense of them either - you'll need the key
- xilswap.py - simply swaps endianness of each 32 bit word. nothing too fancy
- pcap_dump_tool - a bare metal ARM tool for zynq bitstream readback. it saves the currently loaded
bitstream to emmc. it's bare metal because the xilinx linux driver had a bug that prevented it
from working correctly. additionally, some low-level steps needed to be taken to ensure the
readback was not corrupted. comments explain each step. you will need to adjust the parameters
based on the fpga part you have, however. also it needs to be built with the xilinx toolchain

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pcap_dump_tool/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
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pcap_dump_tool/.settings/org.eclipse.core.resources.prefs Normal file
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eclipse.preferences.version=1
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1
pcap_dump_tool/src/README.txt Normal file
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Empty application. Add your own sources.

2
pcap_dump_tool/src/Xilinx.spec Normal file
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*startfile:
crti%O%s crtbegin%O%s

287
pcap_dump_tool/src/lscript.ld Normal file
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
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/* Specify the default entry point to the program */
ENTRY(_vector_table)
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SECTIONS
{
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KEEP (*(.vectors))
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*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0
.got : {
*(.got)
} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0
_end = .;
}

387
pcap_dump_tool/src/xuartps_hello_world_example.c Normal file
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@ -0,0 +1,387 @@
#include <stdio.h>
#include <string.h>
#include <sleep.h>
// xilinx includes
#include <xparameters.h>
#include <xil_printf.h>
#include <xuartps.h>
#include <xil_exception.h>
// fpga driver
#include <xdevcfg.h>
// filesystem driver
#include <xsdps.h>
#include <ff.h>
#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
// slcr registers
// write protect lock
#define SLCR_LOCK 0xF8000004
// write protect unlock
#define SLCR_UNLOCK 0xF8000008
// level shifters enable
#define SLCR_LVL_SHFTR_EN 0xF8000900
// pcap clock control
#define SLCR_PCAP_CLK_CTRL (XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168)
// pcap clock enable mask
#define SLCR_PCAP_CLK_CTRL_EN_MASK 0x1
// slcr lock magic number
#define SLCR_LOCK_VAL 0x767B
// slcr unlock magic number
#define SLCR_UNLOCK_VAL 0xDF0D
// this fpga (zynq 7000 -7s-clg400) has 5152 frames of 101 words each
// words are 32 bit
// plus one pad frame
//#define FRAMES (5152 + 1)
//#define FRAMES (1280 + 2) // BRAM frames plus pad
//#define FRAMES (256+2)
#define FRAMES 1280
//#define START_FAR (0x00800000)
#define RANDOM_FAR (0x008001a2)
//#define FRAMES 3
#define WORDS_PER_FRAME 101
#define MAKE_FAR(bottom_top, row_addr, col_addr, minor_addr) \
(0x00800000 | (bottom_top << 22) | (row_addr << 17) | (col_addr << 7) | minor_addr)
int bitstream_dump(XDcfg* DcfgInstance, u16 DeviceId);
void bitstream_print();
void bitstream_sdcard_write();
XDcfg DcfgInstance;
XUartPs Uart_Ps;
// readback bitstream and commands buffers
// all frames of bram, plus 2 frames of padding in the beginning
// plus 2 frames of padding between top and bottom sections
#define READBACK_SIZE_WORDS (WORDS_PER_FRAME * (FRAMES + 2 + 2))
volatile u32 readback_buffer[READBACK_SIZE_WORDS];
#define READBACK_EXPORT_START ((void*) &readback_buffer[0])
#define READBACK_EXPORT_SIZE (READBACK_SIZE_WORDS * sizeof(uint32_t))
#define rb_seq1_length (sizeof(readback_seq1)/sizeof(u32))
static u32 readback_seq1[] = {
0xFFFFFFFF, //Dummy
0x000000BB, //Bus width sync
0x11220044, //Bus width detect
0xFFFFFFFF, //Dummy
0xAA995566, //Sync
0x20000000, //NOP
0x30002001, //Write to FAR
MAKE_FAR(0, 0, 0, 0), // READ BRAM
0x30008001, //Write to CMD 0x20000000, //NOP
0x0000000B, //Shutdown 0x20000000, //NOP
0x20000000, //NOP
0x30008001, //Write to CMD
0x00000007, //Reset CRC command
0x20000000, //NOP
0x20000000, //NOP
0x20000000, //NOP
0x20000000, //NOP
0x20000000, //NOP
0x20000000, //NOP
0x30008001, //Write to CMD
0x00000004, //RCFG command
//32 NOPs
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, //NOP
0x28006000, //Type 1 read FDRO
0x48000000 | READBACK_SIZE_WORDS, // Type 2, size in words to read
0x20000000, 0x20000000, // NOP
0x30008001, // WRITE CMD
0x0000000d, // DESYNC
//400 NOPs
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
};
int main(void) {
int status;
Xil_DCacheFlush();
Xil_DCacheInvalidate();
Xil_DCacheDisable();
Xil_ICacheInvalidate();
Xil_ICacheDisable();
Xil_ExceptionDisable();
status = bitstream_dump(&DcfgInstance, DCFG_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("Failed!!!\r\n");
return XST_FAILURE;
}
xil_printf("Successfully ran FPGA dump\r\n");
return XST_SUCCESS;
}
int bitstream_dump(XDcfg *DcfgInstPtr, u16 DeviceId) {
int Status;
u32 IntrStsReg = 0;
u32 StatusReg;
u32 pcap_clk_reg;
XDcfg_Config *ConfigPtr;
XUartPs_Config *Config;
/*
* Initialize the UART driver so that it's ready to use
* Look up the configuration in the config table and then initialize it.
*/
Config = XUartPs_LookupConfig(UART_DEVICE_ID);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XUartPs_CfgInitialize(&Uart_Ps, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XUartPs_SetBaudRate(&Uart_Ps, 115200);
/*
* Initialize the Device Configuration Interface driver.
*/
ConfigPtr = XDcfg_LookupConfig(DeviceId);
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, ConfigPtr->BaseAddr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XDcfg_SelfTest(DcfgInstPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the pcap clock.
*/
pcap_clk_reg = Xil_In32(SLCR_PCAP_CLK_CTRL);
Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL);
// enable pcap clock and set divisor to 0xF
// THIS IS IMPORTANT
// the pcap clock needs to be slowed down or it overflows the fifo
Xil_Out32(SLCR_PCAP_CLK_CTRL, (pcap_clk_reg | SLCR_PCAP_CLK_CTRL_EN_MASK | (0xF << 8)));
Xil_Out32(SLCR_UNLOCK, SLCR_LOCK_VAL);
/*
* Select PCAP interface for bitstream readback
*/
XDcfg_EnablePCAP(DcfgInstPtr);
XDcfg_SetControlRegister(DcfgInstPtr, XDCFG_CTRL_PCAP_MODE_MASK);
XDcfg_IntrClear(DcfgInstPtr, (XDCFG_IXR_PCFG_DONE_MASK |
XDCFG_IXR_D_P_DONE_MASK |
XDCFG_IXR_DMA_DONE_MASK));
/* Check if DMA command queue is full */
StatusReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
return XST_FAILURE;
}
if (StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) {
xil_printf("????\r\n");
return XST_FAILURE;
}
/*
* Readback bitstream
*/
XDcfg_Transfer(DcfgInstPtr, (u32 *)readback_seq1, rb_seq1_length,
(u32 *)readback_buffer, WORDS_PER_FRAME*(FRAMES + 2),
XDCFG_PCAP_READBACK);
/* Poll IXR_DMA_DONE */
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) !=
XDCFG_IXR_DMA_DONE_MASK) {
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
}
// why do we need to do this 2x? nobody knows
for (size_t i = 0; i < 2; i++) {
/* Poll IXR_D_P_DONE */
while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) !=
XDCFG_IXR_D_P_DONE_MASK) {
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
}
// clear interrupts
XDcfg_IntrClear(DcfgInstPtr,
(XDCFG_IXR_D_P_DONE_MASK | XDCFG_IXR_DMA_DONE_MASK));
asm volatile("":::"memory");
usleep(10);
}
asm volatile("":::"memory");
#define checkreg(reg, msk) if (reg & msk) { \
xil_printf("register check failure: %s %s\r\n", #reg, #msk); \
return XST_FAILURE; \
}
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
StatusReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
asm volatile("":::"memory");
checkreg(IntrStsReg, XDCFG_IXR_D_P_DONE_MASK);
checkreg(IntrStsReg, XDCFG_IXR_DMA_DONE_MASK);
// checkreg(IntrStsReg, XDCFG_IXR_AXI_WTO_MASK);
// we're not supplying data fast enough? idk should be fine
if (IntrStsReg & XDCFG_IXR_AXI_WTO_MASK) {
XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_AXI_WTO_MASK);
}
checkreg(IntrStsReg, XDCFG_IXR_AXI_WERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_AXI_RTO_MASK);
checkreg(IntrStsReg, XDCFG_IXR_AXI_RERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_RX_FIFO_OV_MASK);
checkreg(IntrStsReg, XDCFG_IXR_DMA_CMD_ERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_DMA_Q_OV_MASK);
checkreg(IntrStsReg, XDCFG_IXR_P2D_LEN_ERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_PCFG_HMAC_ERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_PCFG_SEU_ERR_MASK);
checkreg(IntrStsReg, XDCFG_IXR_PCFG_POR_B_MASK);
// checkreg(IntrStsReg, XDCFG_IXR_PCFG_CFG_RST_MASK);
checkreg(StatusReg, XDCFG_STATUS_DMA_CMD_Q_F_MASK);
checkreg(StatusReg, XDCFG_STATUS_SECURE_RST_MASK);
checkreg(StatusReg, XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK);
// checkreg(StatusReg, XDCFG_STATUS_DMA_DONE_CNT_MASK);
asm volatile("":::"memory");
xil_printf("Bitstream readback complete\r\n");
// print bitstream
//bitstream_print();
bitstream_sdcard_write();
/*
TO-DO: Restart fabric.
we don't rly care just reset the board with the button lol
*/
return XST_SUCCESS;
}
void bitstream_print() {
xil_printf("Print Bitstream\r\n");
int i;
for(i=0; i< WORDS_PER_FRAME * FRAMES; i++) {
xil_printf("%08x", readback_buffer[i]);
xil_printf("\r\n");
}
xil_printf("Finished printing bitstream!\r\n");
}
void bitstream_sdcard_write() {
xil_printf("Writing bitstream to file\r\n");
#define chk(msg) \
if (res != FR_OK) {\
xil_printf("error: %s %d\r\n", msg, res);\
return;\
} else { xil_printf("%s success\r\n", msg); }
FIL fil;
FATFS fatfs;
TCHAR write_filename[32];
FRESULT res = f_mount(&fatfs, "0:/", 0);
chk("mount");
xil_printf("checking for a new filename\r\n");
int found = 0;
for (uint32_t i = 0; i < 26; i++) {
static const char* alph = "abcdefghijklmnopqrstuvwxyz";
memset(write_filename, 0, sizeof(write_filename));
snprintf(write_filename, sizeof(write_filename), "0:/readbak%c.bin", alph[i]);
memset(&fil, 0, sizeof(fil));
res = f_open(&fil, write_filename, FA_READ | FA_OPEN_EXISTING);
if (res != FR_OK) {
xil_printf("found free file: %s\r\n", write_filename);
found = 1;
break;
}
xil_printf("used: %s\r\n", write_filename);
f_close(&fil);
}
if (!found) {
xil_printf("didn't find a filename to use\r\n");
return;
}
memset(&fil, 0, sizeof(fil));
res = f_open(&fil, write_filename, FA_CREATE_ALWAYS | FA_WRITE);
chk("open");
res = f_lseek(&fil, 0);
chk("lseek");
UINT bytes_written;
res = f_write(&fil, READBACK_EXPORT_START, READBACK_EXPORT_SIZE, &bytes_written);
chk("write");
if (bytes_written != READBACK_EXPORT_SIZE) {
xil_printf("incomplete write, wrote %u bytes\n", bytes_written);
}
res = f_sync(&fil);
chk("sync");
res = f_close(&fil);
chk("close");
res = f_mount(NULL, "0:/", 0);
chk("unmount");
}

230
xilbitstream.py Executable file
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#!/usr/bin/env python3
import struct
from typing import NamedTuple, Union
from enum import IntEnum
import sys
WORD_BE = struct.Struct(">I")
WORD_LE = struct.Struct("<I")
WORD = WORD_BE
WORD_SWAPPED = False
def _pack_word(word: int) -> bytes:
return WORD.pack((word,))
def _unpack_word(word: bytes) -> int:
return WORD.unpack(word)[0]
def swap_endian() -> None:
global WORD_SWAPPED
global WORD
if WORD_SWAPPED:
raise Exception("Swapping enddianness twice oops")
WORD_SWAPPED = True
WORD = WORD_LE
def _hex_pad(word: int) -> str:
return "{0:#0{1}x}".format(word, 10)
DUMMY_PAD = 0xFFFFFFFF
BUS_WIDTH_DET_1 = 0x000000BB
BUS_WIDTH_DET_1_EXCEPT_WRONG_WAY = 0xBB000000
BUS_WIDTH_DET_2 = 0x11220044
SYNC_WORD = 0xAA995566
PACKET_TYPE_1 = 1
PACKET_TYPE_2 = 2
CFG_FRAME_WORD_LENGTH = 101
class MiscWord(IntEnum):
DUMMY_PAD = 1
BUS_WIDTH_DET_1 = 2
BUS_WIDTH_DET_2 = 3
SYNC_WORD = 4
class PacketOp(IntEnum):
NOP = 0
READ = 1
WRITE = 2
RESERVED = 3
class Register(IntEnum):
CRC = 0b00000
FAR = 0b00001
FDRI = 0b00010
FDRO = 0b00011
CMD = 0b00100
CTL0 = 0b00101
MASK = 0b00110
STAT = 0b00111
LOUT = 0b01000
COR0 = 0b01001
MFWR = 0b01010
CBC = 0b01011
IDCODE = 0b01100
AXSS = 0b01101
COR1 = 0b01110
WBSTAR = 0b10000
TIMER = 0b10001
BOOTSTS= 0b10110
CTL1 = 0b11000
BSPI = 0b11111
UNDOC_1= 0b10011 # Documentation? what's that lol ~ Xilinx, probably
class FarType(IntEnum):
FABRIC = 0
BRAM = 1
CFG_CLB = 2
UNDOC_1 = 7 # And again
class FarValue(NamedTuple):
blocktype: FarType
bottom_top: int
row_addr: int
col_addr: int
minor_addr: int
class CmdValue(IntEnum):
NULL = 0b00000
WCFG = 0b00001
MFW = 0b00010
DGHIGH_LFRM = 0b00011
RCFG = 0b00100
START = 0b00101
AGHIGH = 0b01000
RCRC = 0b00111
SWITCH = 0b01001
GRESTORE = 0b01010
SHUTDOWN = 0b01011
DESYNC = 0b01101
class Type1(NamedTuple):
op: PacketOp
address: Register
word_count: int
class Type2(NamedTuple):
op: PacketOp
word_count: int
def _skip_xil_header(data: bytes) -> bytes:
# I really don't know what in the nondeterministic fuck is going on with this
# there's a size field at the end that might be important
# see http://www.pldtool.com/pdf/fmt_xilinxbit.pdf
for i in range(len(data) - 4):
word = _unpack_word(data[i:i+4])
if word == DUMMY_PAD:
if i >= 4:
# we found a header
print(".......... xilinx header")
data_len = _unpack_word(data[i-4:i])
# safety check the size field
assert data_len == len(data) - i
else:
# no header
assert i == 0
# return start of bitstream data
return i
raise Exception("Didn't find pad word!")
def _parse_far_word(word: int) -> FarValue:
try:
blk_type = (word >> 23) & 0b111
bottom_top = (word >> 22) & 0b1
row_addr = (word >> 17) & 0b11111
col_addr = (word >> 7) & 0b1111111111
minor_addr = word & 0b1111111
return FarValue(FarType(blk_type), bottom_top, row_addr, col_addr, minor_addr)
except:
raise Exception("Invalid FAR value: " + _hex_pad(word))
def _parse_cmd_word(word: int) -> CmdValue:
try:
return CmdValue(word)
except:
raise Exception("Invalid command value: " + _hex_pad(word))
def _parse_next_word(word: int) -> Union[MiscWord, Type1, Type2]:
try:
if word == DUMMY_PAD:
return MiscWord.DUMMY_PAD
elif word == BUS_WIDTH_DET_1_EXCEPT_WRONG_WAY:
swap_endian()
return MiscWord.BUS_WIDTH_DET_1
elif word == BUS_WIDTH_DET_1:
return MiscWord.BUS_WIDTH_DET_1
elif word == BUS_WIDTH_DET_2:
return MiscWord.BUS_WIDTH_DET_2
elif word == SYNC_WORD:
return MiscWord.SYNC_WORD
else:
header_bits = (word >> 29) & 0b111
opcode = (word >> 27) & 0b11
if header_bits == PACKET_TYPE_1:
addr = (word >> 13) & 0b11111
count = word & 0b1111111111
return Type1(PacketOp(opcode), Register(addr), count)
elif header_bits == PACKET_TYPE_2:
count = word & 0b11111111111111111111111111
return Type2(PacketOp(opcode), count)
raise Exception()
except:
raise Exception("Unknown word: " + _hex_pad(word))
def parse_bitstream(data: bytes) -> None:
i = _skip_xil_header(data)
data_counter = 0
last_far = None
bram_addrs = set()
while i < len(data):
word = _unpack_word(data[i:i+4])
obj = _parse_next_word(word)
print(_hex_pad(word), obj)
i += 4
if isinstance(obj, Type1) and obj.address == Register.FAR:
assert obj.word_count == 1
dat_word = _unpack_word(data[i:i+4])
last_far = _parse_far_word(dat_word)
if last_far.blocktype == FarType.BRAM:
bram_addrs.add(dat_word)
print(_hex_pad(dat_word), last_far)
i += 4
elif isinstance(obj, Type1) and obj.address == Register.CMD:
assert obj.word_count == 1
dat_word = _unpack_word(data[i:i+4])
print(_hex_pad(dat_word), _parse_cmd_word(dat_word))
i += 4
elif isinstance(obj, Type1) or isinstance(obj, Type2):
if obj.word_count > 0:
if obj.word_count < 4:
for j in range(obj.word_count):
dat_word = _unpack_word(data[i+j*4:i+j*4+4])
print(_hex_pad(dat_word), "data")
else:
l = f"{data_counter}"
if last_far is not None and last_far.blocktype == FarType.BRAM:
l = f"_bram_{last_far.bottom_top}_{last_far.row_addr}_{last_far.col_addr}_{last_far.minor_addr}"
out_file = f"{sys.argv[1]}-frames-{l}.dat"
data_counter += 1
print("..........", obj.word_count, "words (written to ", out_file, ")")
with open(out_file, "wb") as f:
f.write(data[i:i+obj.word_count*4])
i += obj.word_count * 4
if i != len(data):
raise Exception("Desync??")
if __name__ == "__main__":
if len(sys.argv) < 2:
print("Usage: ./xilbitstream.py <bitstream-file>")
sys.exit()
with open(sys.argv[1], "rb") as f:
data = f.read()
parse_bitstream(data)

25
xilswap.py Executable file
View File

@ -0,0 +1,25 @@
#!/usr/bin/env python3
import sys
import struct
WORD_BE = struct.Struct(">I")
WORD_LE = struct.Struct("<I")
if __name__ == "__main__":
if len(sys.argv) < 3:
print("usage: xilswap.py <in> <out>")
with open(sys.argv[1], "rb") as f:
data = f.read()
assert(len(data) % 4 == 0)
print("total", len(data)//4)
with open(sys.argv[2], "wb") as f:
for i in range(len(data)//4):
word = WORD_BE.unpack(data[i*4:i*4+4])[0]
f.write(WORD_LE.pack(word))
if i % 10000 == 0:
print(i, "/", len(data)//4)