stm32f072disco BSP added
This commit is contained in:
Peter Lawrence
parent
1b937fa4ae
commit
2675203a9c
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@ -0,0 +1,495 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Peter Lawrence
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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As written, pins PC6, PC7, PC8 were chosen as SWCLK, SWDIO, and RESETn respectively.
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These pins map to LEDs on the STM32F072DISCO, but can be customized as needed.
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*/
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#ifndef __DAP_CONFIG_H__
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#define __DAP_CONFIG_H__
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
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\ingroup DAP_ConfigIO_gr
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@{
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Provides definitions about the hardware and configuration of the Debug Unit.
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This information includes:
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- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
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- Debug Unit Identification strings (Vendor, Product, Serial Number).
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- Debug Unit communication packet size.
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- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
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- Optional information about a connected Target Device (for Evaluation Boards).
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*/
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#include "cmsis_compiler.h"
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#include "bsp/board.h"
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#include <stm32f0xx_hal.h>
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/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
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/// This value is used to calculate the SWD/JTAG clock speed.
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#define CPU_CLOCK 48000000U ///< Specifies the CPU Clock in Hz.
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/// Number of processor cycles for I/O Port write operations.
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/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
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/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
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/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
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/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
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/// required.
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#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
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/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
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/// Indicate that JTAG communication mode is available at the Debug Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
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/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
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/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
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#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
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/// Default communication mode on the Debug Access Port.
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/// Used for the command \ref DAP_Connect when Port Default mode is selected.
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#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
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/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
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/// Used to initialize the default SWD/JTAG clock frequency.
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/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
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#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
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/// Maximum Package Size for Command and Response data.
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/// This configuration settings is used to optimize the communication performance with the
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/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
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/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
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#define DAP_PACKET_SIZE CFG_TUD_HID_EP_BUFSIZE ///< Specifies Packet Size in bytes.
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/// Maximum Package Buffers for Command and Response data.
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/// This configuration settings is used to optimize the communication performance with the
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/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
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/// setting can be reduced (valid range is 1 .. 255).
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#define DAP_PACKET_COUNT 1U ///< Specifies number of packets buffered.
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/// Indicate that UART Serial Wire Output (SWO) trace is available.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available.
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/// Maximum SWO UART Baudrate.
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#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
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/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
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/// SWO Trace Buffer Size.
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#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n).
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/// SWO Streaming Trace.
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#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
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/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
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#define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported).
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/// Debug Unit is connected to fixed Target Device.
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/// The Debug Unit may be part of an evaluation board and always connected to a fixed
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/// known device. In this case a Device Vendor and Device Name string is stored which
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/// may be used by the debugger or IDE to configure device parameters.
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#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
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#if TARGET_DEVICE_FIXED
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#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor
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#define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device
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#endif
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#include "DAP.h"
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/** Get Vendor ID string.
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\param str Pointer to buffer to store the string.
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\return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
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(void)str;
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return (0U);
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}
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/** Get Product ID string.
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\param str Pointer to buffer to store the string.
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\return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
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(void)str;
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return (0U);
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}
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/** Get Serial Number string.
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\param str Pointer to buffer to store the string.
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\return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
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(void)str;
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return (0U);
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}
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///@}
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/* these macros are used by the API functions further below */
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#define CLK_PIN 6
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#define DATA_PIN 7
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#define RESET_PIN 8
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#define CLK_LOW { GPIOC->BSRR = (1UL << CLK_PIN) << 16; }
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#define CLK_HIGH { GPIOC->BSRR = (1UL << CLK_PIN) << 0; }
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#define CLK_ENABLE { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (CLK_PIN * 2))) | (0x1 << (CLK_PIN * 2)) ); }
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#define CLK_HIZ { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (CLK_PIN * 2))) ); }
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#define DATA_LOW { GPIOC->BSRR = (1UL << DATA_PIN) << 16; }
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#define DATA_HIGH { GPIOC->BSRR = (1UL << DATA_PIN) << 0; }
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#define DATA_ENABLE { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (DATA_PIN * 2))) | (0x1 << (DATA_PIN * 2)) ); }
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#define DATA_HIZ { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (DATA_PIN * 2))) ); }
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#define RESET_LOW { GPIOC->BSRR = (1UL << RESET_PIN) << 16; }
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#define RESET_HIGH { GPIOC->BSRR = (1UL << RESET_PIN) << 0; }
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#define RESET_ENABLE { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (RESET_PIN * 2))) | (0x1 << (RESET_PIN * 2)) ); }
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#define RESET_HIZ { GPIOC->MODER = ( (GPIOC->MODER & ~(0x3 << (RESET_PIN * 2))) ); }
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#define SWDIO_INIT { __HAL_RCC_GPIOC_CLK_ENABLE(); }
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#define DATA_READ (GPIOC->IDR & (1UL << DATA_PIN))
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#define CLK_READ (GPIOC->IDR & (1UL << CLK_PIN))
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#define RESET_READ (GPIOC->IDR & (1UL << RESET_PIN))
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
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\ingroup DAP_ConfigIO_gr
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@{
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Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
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and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
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interface of a device. The following I/O Pins are provided:
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JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
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---------------------------- | -------------------- | ---------------------------------------------
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TCK: Test Clock | SWCLK: Clock | Output Push/Pull
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TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
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TDI: Test Data Input | | Output Push/Pull
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TDO: Test Data Output | | Input
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nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
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nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
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DAP Hardware I/O Pin Access Functions
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-------------------------------------
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The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
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these I/O Pins.
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For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
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This functions are provided to achieve faster I/O that is possible with some advanced GPIO
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peripherals that can independently write/read a single I/O pin without affecting any other pins
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of the same I/O port. The following SWDIO I/O Pin functions are provided:
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- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
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- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
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- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
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- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
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*/
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// Configure DAP I/O pins ------------------------------
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/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
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Configures the DAP Hardware I/O pins for JTAG mode:
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- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
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- TDO to input mode.
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*/
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__STATIC_INLINE void PORT_JTAG_SETUP (void) {
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;
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}
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/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
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Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
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- SWCLK, SWDIO, nRESET to output mode and set to default high level.
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- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
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*/
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__STATIC_INLINE void PORT_SWD_SETUP (void) {
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CLK_ENABLE;
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DATA_ENABLE;
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SWDIO_INIT;
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CLK_HIGH; DATA_HIGH;
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}
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/** Disable JTAG/SWD I/O Pins.
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Disables the DAP Hardware I/O pins which configures:
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- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
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*/
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__STATIC_INLINE void PORT_OFF (void) {
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CLK_HIZ;
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DATA_HIZ;
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RESET_HIZ;
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}
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// SWCLK/TCK I/O pin -------------------------------------
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/** SWCLK/TCK I/O pin: Get Input.
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\return Current status of the SWCLK/TCK DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
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return (CLK_READ) ? 1 : 0;
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}
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/** SWCLK/TCK I/O pin: Set Output to High.
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Set the SWCLK/TCK DAP hardware I/O pin to high level.
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*/
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__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
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CLK_HIGH;
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}
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/** SWCLK/TCK I/O pin: Set Output to Low.
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Set the SWCLK/TCK DAP hardware I/O pin to low level.
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*/
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__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
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CLK_LOW;
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}
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// SWDIO/TMS Pin I/O --------------------------------------
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/** SWDIO/TMS I/O pin: Get Input.
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\return Current status of the SWDIO/TMS DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
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return (DATA_READ) ? 1 : 0;
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}
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/** SWDIO/TMS I/O pin: Set Output to High.
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Set the SWDIO/TMS DAP hardware I/O pin to high level.
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*/
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__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
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DATA_HIGH;
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}
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/** SWDIO/TMS I/O pin: Set Output to Low.
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Set the SWDIO/TMS DAP hardware I/O pin to low level.
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*/
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__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
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DATA_LOW;
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}
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/** SWDIO I/O pin: Get Input (used in SWD mode only).
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\return Current status of the SWDIO DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
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return (DATA_READ) ? 1 : 0;
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}
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/** SWDIO I/O pin: Set Output (used in SWD mode only).
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\param bit Output value for the SWDIO DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
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if (bit & 1) { DATA_HIGH; } else { DATA_LOW; }
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}
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/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
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Configure the SWDIO DAP hardware I/O pin to output mode. This function is
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called prior \ref PIN_SWDIO_OUT function calls.
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*/
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__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
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DATA_ENABLE;
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}
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/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
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Configure the SWDIO DAP hardware I/O pin to input mode. This function is
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called prior \ref PIN_SWDIO_IN function calls.
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*/
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__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
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DATA_HIZ;
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}
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// TDI Pin I/O ---------------------------------------------
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/** TDI I/O pin: Get Input.
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\return Current status of the TDI DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
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return (0U);
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}
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/** TDI I/O pin: Set Output.
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\param bit Output value for the TDI DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
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;
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}
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// TDO Pin I/O ---------------------------------------------
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/** TDO I/O pin: Get Input.
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\return Current status of the TDO DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
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return (0U);
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}
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// nTRST Pin I/O -------------------------------------------
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/** nTRST I/O pin: Get Input.
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\return Current status of the nTRST DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
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return (0U);
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}
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/** nTRST I/O pin: Set Output.
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\param bit JTAG TRST Test Reset pin status:
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- 0: issue a JTAG TRST Test Reset.
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- 1: release JTAG TRST Test Reset.
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*/
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__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
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(void)bit;
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}
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// nRESET Pin I/O------------------------------------------
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/** nRESET I/O pin: Get Input.
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\return Current status of the nRESET DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
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return (RESET_READ) ? 1 : 0;
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}
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/** nRESET I/O pin: Set Output.
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\param bit target device hardware reset pin status:
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- 0: issue a device hardware reset.
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- 1: release device hardware reset.
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*/
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__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
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if (bit & 1) { RESET_HIGH; } else { RESET_LOW; }
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}
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///@}
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
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\ingroup DAP_ConfigIO_gr
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@{
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CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
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It is recommended to provide the following LEDs for status indication:
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- Connect LED: is active when the DAP hardware is connected to a debugger.
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- Running LED: is active when the debugger has put the target device into running state.
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*/
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/** Debug Unit: Set status of Connected LED.
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\param bit status of the Connect LED.
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- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
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- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
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*/
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__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
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(void)bit;
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}
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/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
|
||||
(void)bit;
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Access function for Test Domain Timer.
|
||||
|
||||
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
|
||||
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
|
||||
|
||||
*/
|
||||
|
||||
/** Get timestamp of Test Domain Timer.
|
||||
\return Current timestamp value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
|
||||
#if TIMESTAMP_CLOCK > 0
|
||||
return (DWT->CYCCNT);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
__STATIC_INLINE void DAP_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t RESET_TARGET (void) {
|
||||
return (0U); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
Loading…
Reference in New Issue