glue code part of the spi kernel module, actual xfers is for tomorrow
This commit is contained in:
parent
41d352af3d
commit
444d805f0b
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@ -1,5 +1,5 @@
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obj-m := dmj.o dmj-char.o i2c-dmj.o spi-dmj.c
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obj-m := dmj.o dmj-char.o i2c-dmj.o #spi-dmj.c
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KDIR := /lib/modules/$(shell uname -r)/build
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PWD := $(shell pwd)
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@ -0,0 +1,544 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for the DapperMime-JTAG USB multitool: USB-SPI adapter
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*
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* Copyright (c) 2021 sys64738 and haskal
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*
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* Adapted from:
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* spi-dln2.c, Copyright (c) 2014 Intel Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/pm_runtime.h>
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#include <asm/unaligned.h>
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#if 0
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#include <linux/mfd/dmj.h>
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#else
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#include "dmj.h"
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#endif
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#define HARDWARE_NAME "DapperMime-JTAG"
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#define DMJ_SPI_CMD_NOP 0x00
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#define DMJ_SPI_CMD_Q_IFACE 0x01
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#define DMJ_SPI_CMD_Q_CMDMAP 0x02
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#define DMJ_SPI_CMD_Q_PGMNAME 0x03
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#define DMJ_SPI_CMD_Q_SERBUF 0x04
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#define DMJ_SPI_CMD_Q_BUSTYPE 0x05
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#define DMJ_SPI_CMD_Q_CHIPSIZE 0x06
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#define DMJ_SPI_CMD_Q_OPBUF 0x07
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#define DMJ_SPI_CMD_Q_WRNMAXLEN 0x08
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#define DMJ_SPI_CMD_R_BYTE 0x09
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#define DMJ_SPI_CMD_R_NBYTES 0x0a
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#define DMJ_SPI_CMD_O_INIT 0x0b
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#define DMJ_SPI_CMD_O_WRITEB 0x0c
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#define DMJ_SPI_CMD_O_WRITEN 0x0d
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#define DMJ_SPI_CMD_O_DELAY 0x0e
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#define DMJ_SPI_CMD_O_EXEC 0x0f
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#define DMJ_SPI_CMD_SYNCNOP 0x10
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#define DMJ_SPI_CMD_Q_RDNMAXLEN 0x11
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#define DMJ_SPI_CMD_S_BUSTYPE 0x12
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#define DMJ_SPI_CMD_SPIOP 0x13
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#define DMJ_SPI_CMD_S_SPI_FREQ 0x14
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#define DMJ_SPI_CMD_S_PINSTATE 0x15
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#define DMJ_SPI_CMD_Q_SPI_CAPS 0x40
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#define DMJ_SPI_CMD_S_SPI_CHIPN 0x41
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#define DMJ_SPI_CMD_S_SPI_SETCS 0x42
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#define DMJ_SPI_CMD_S_SPI_FLAGS 0x43
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#define DMJ_SPI_CMD_S_SPI_BPW 0x44
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#define DMJ_SPI_CMD_SPI_READ 0x45
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#define DMJ_SPI_CMD_SPI_WRITE 0x46
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#define DMJ_SPI_CMD_SPI_RDWR 0x47
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#define SERPROG_IFACE_VERSION 0x0001
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static const uint8_t reqd_cmds[] = {
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DMJ_SPI_CMD_NOP, DMJ_SPI_CMD_Q_IFACE, DMJ_SPI_CMD_Q_CMDMAP,
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DMJ_SPI_CMD_Q_WRNMAXLEN, DMJ_SPI_CMD_Q_RDNMAXLEN,
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DMJ_SPI_CMD_S_SPI_FREQ, DMJ_SPI_CMD_S_PINSTATE, /*DMJ_SPI_CMD_SPIOP,*/
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DMJ_SPI_CMD_Q_SPI_CAPS, DMJ_SPI_CMD_S_SPI_CHIPN, DMJ_SPI_CMD_S_SPI_FLAGS,
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DMJ_SPI_CMD_S_SPI_BPW, DMJ_SPI_CMD_S_SPI_SETCS,
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/*DMJ_SPI_CMD_SPI_READ, DMJ_SPI_CMD_SPI_WRITE, DMJ_SPI_CMD_SPI_RDWR,*/
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};
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#define DMJ_SPI_ACK 0x06
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#define DMJ_SPI_NAK 0x15
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#define DMJ_SPI_S_FLG_CPHA (1<<0)
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#define DMJ_SPI_S_FLG_CPOL (1<<1)
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#define DMJ_SPI_S_FLG_STDSPI (0<<2)
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#define DMJ_SPI_S_FLG_TISSP (1<<2)
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#define DMJ_SPI_S_FLG_MICROW (2<<2)
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#define DMJ_SPI_S_FLG_MSBFST (0<<4)
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#define DMJ_SPI_S_FLG_LSBFST (1<<4)
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#define DMJ_SPI_S_FLG_CSACLO (0<<5)
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#define DMJ_SPI_S_FLG_CSACHI (1<<5)
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#define DMJ_SPI_S_FLG_3WIRE (1<<6)
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#define DMJ_SPI_S_CAP_CPHA_HI (1<<0)
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#define DMJ_SPI_S_CAP_CPHA_LO (1<<1)
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#define DMJ_SPI_S_CAP_CPOL_HI (1<<2)
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#define DMJ_SPI_S_CAP_CPOL_LO (1<<3)
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#define DMJ_SPI_S_CAP_STDSPI (1<<4)
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#define DMJ_SPI_S_CAP_TISSP (1<<5)
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#define DMJ_SPI_S_CAP_MICROW (1<<6)
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#define DMJ_SPI_S_CAP_MSBFST (1<<7)
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#define DMJ_SPI_S_CAP_LSBFST (1<<8)
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#define DMJ_SPI_S_CAP_CSACHI (1<<9)
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#define DMJ_SPI_S_CAP_3WIRE (1<<10)
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struct dmj_spi_caps {
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uint32_t freq_min, freq_max;
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uint16_t flgcaps;
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uint8_t num_cs, min_bpw, max_bpw;
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};
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struct dmj_spi_dev_sett {
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/* does not have to be guarded with a spinlock, as the kernel already
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* serializes transfer_one/set_cs calls */
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uint32_t freq;
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uint8_t flags, bpw;
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uint8_t cs;
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};
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struct dmj_spi {
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struct platform_device *pdev;
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struct spi_controller *spictl;
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uint8_t cmdmap[32];
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struct dmj_spi_caps caps;
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uint8_t csmask;
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struct dmj_spi_dev_sett devsettings[8];
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uint32_t wrnmaxlen, rdnmaxlen;
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spinlock_t csmap_lock;
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};
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static bool has_cmd(struct dmj_spi *dmjs, int cmd)
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{
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int byteind = cmd >> 3, bitind = cmd & 7;
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return dmjs->cmdmap[byteind] & (1 << bitind);
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}
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static uint8_t kernmode_to_flags(uint16_t caps, int mode)
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{
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uint8_t ret = mode & 3; /* bottom 2 bits are the SPI mode (CPHA & CPOL) */
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if (mode & SPI_LSB_FIRST) ret |= DMJ_SPI_S_FLG_LSBFST;
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else ret |= DMJ_SPI_S_FLG_MSBFST;
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if (mode & SPI_CS_HIGH) ret |= DMJ_SPI_S_FLG_CSACHI;
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else ret |= DMJ_SPI_S_FLG_CSACLO;
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if (mode & SPI_3WIRE) ret |= DMJ_SPI_SL_FLG_3WIRE;
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/* need some defaults for other stuff */
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if (caps & DMJ_SPI_S_CAP_STDSPI) ret |= DMJ_SPI_S_FLG_STDSPI;
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else if (caps & DMJ_SPI_S_CAP_TISSP) ret |= DMJ_SPI_S_FLG_TISSP;
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else if (caps & DMJ_SPI_S_CAP_MICROW) ret |= DMJ_SPI_S_FLG_MICROW;
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else ret |= DMJ_SPI_S_FLG_STDSPI; /* shrug */
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return ret;
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}
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static int devcaps_to_kernmode(uint16_t caps)
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{
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int ret;
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ret = caps & 3; /* SPI mode (CPHA & CPOL) bits */
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if (caps & DMJ_SPI_S_CAP_LSBFST) ret |= SPI_LB_FIRST;
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if (caps & DMJ_SPI_S_CAP_CSACHI) ret |= SPI_CS_HIGH;
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if (caps & DMJ_SPI_S_CAP_3WIRE) ret |= SPI_3WIRE;
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return ret;
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}
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static int bufconv_to_le(void *dst, const void *src, size_t len_bytes, uint8_t bpw)
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{
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#ifdef __LITTLE_ENDIAN
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memcpy(dst, src, len_bytes);
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#else
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if (bpw > 16) {
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__le32 *dst32 = (__le32 *)dst;
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const uint32_t *src32 = (const uint32_t *)src;
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for (size_t i = 0; i < len_bytes; i += 4, ++dst32, ++src32) {
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*dst32 = cpu_to_le32p(src32);
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}
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} else if (bpw > 8) {
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__le16 *dst16 = (__le16 *)dst;
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const uint16_t *src16 = (const uint16_t *)src;
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for (size_t i = 0; i < len_bytes; i += 2, ++dst16, ++src16) {
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*dst16 = cpu_to_le16p(src16);
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}
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} else {
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memcpy(dst, src, len_bytes);
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}
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#endif
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}
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static int bufconv_from_le(void *dst, const void *src, size_t len_bytes, uint8_t bpw)
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{
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#ifdef __LITTLE_ENDIAN
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memcpy(dst, src, len_bytes);
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#else
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if (bpw > 16) {
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const __le32 *src32 = (const __le32 *)src;
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uint32_t *dst32 = (uint32_t *)dst;
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for (size_t i = 0; i < len_bytes; i += 4, ++dst32, ++src32) {
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*dst32 = get_unaligned_le32(src32);
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}
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} else if (bpw > 8) {
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const __le16 *src16 = (const __le16 *)src;
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uint16_t *dst16 = (uint16_t *)dst;
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for (size_t i = 0; i < len_bytes; i += 2, ++dst16, ++src16) {
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*dst16 = le16_to_cpup(src16);
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}
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} else {
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memcpy(dst, src, len_bytes);
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}
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#endif
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}
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static int dmj_spi_csmask_set(struct dmj_spi *dmjs, uint8_t csmask)
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{
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uint8_t oldcm;
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int ret;
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bool do_csmask = false;
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spin_lock(&dmjs->csmap_lock);
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oldcm = dmjs->csmask;
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if (oldcm != csmask) {
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dmjs->csmask = csmask;
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do_csmask = true;
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}
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spin_unlock(&dmjs->csmap_unlock);
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if (do_csmask) {
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// TODO: send S_SPI_CHIPN
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}
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}
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static int dmj_spi_csmask_set_one(struct dmj_spi *dmjs, uint8_t cs)
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{
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return dmj_spi_csmask_set(dmjs, BIT(cs));
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}
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static int dmj_spi_cs_set(struct dmj_spi *dmjs, int ind, bool lvl)
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{
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if (dmjs->devsettings[ind].cs == (lvl ? 1 : 0))
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return 0;
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// TODO: send S_SPI_SETCS
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}
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static int dmj_spi_get_caps(struct dmj_spi *dmjs); // TODO: check if bpw_min > 0
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static int dmj_spi_set_freq(struct dmj_spi *dmjs, int ind, uint32_t freq)
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{
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if (dmjs->devsettings[ind].freq == freq)
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return 0;
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// TODO: send S_SPI_FREQ
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}
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static int dmj_spi_set_flags(struct dmj_spi *dmjs, int ind, uint8_t flags)
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{
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if (dmjs->devsettings[ind].flags == flags)
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return 0;
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// TODO: send S_SPI_FLAGS
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}
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static int dmj_spi_set_bpw(struct dmj_spi *dmjs, int ind, uint8_t bpw)
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{
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if (dmjs->devsettings[ind].bpw == bpw)
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return 0;
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// TODO: send S_SPI_BPW
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}
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static int dmj_spi_set_pinstate(struct dmj_spi *dmjs, bool pins)
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{
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if (!has_cmd(dmjs, DMJ_SPI_CMD_S_PINSTATE))
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return 0;
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// TODO: do cmd
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}
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static int dmj_spi_check_hw(struct dmj_spi *dmjs)
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{
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/*
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* TODO: check:
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* * NOP, SYNCNOP
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* * Q_IFACE retval (must be SERPROG_IFACE_VERSION)
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* * ^ + SPIOP -or- READ & WRITE support
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* * Q_CMDMAP (cf. reqd_cmds)
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* * RDNMAXLEN, WRNMAXLEN
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*/
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}
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static int dmj_spi_do_read(struct dmj_spi *dmjs, void *data, size_t len)
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{
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if (has_cmd(dmjs, DMJ_SPI_CMD_SPI_READ)) {
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/* TODO: do SPI_READ */
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} else {
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/* TODO: do SPIOP */
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}
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}
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static int dmj_spi_do_write(struct dmj_spi *dmjs, const void *data, size_t len)
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{
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if (has_cmd(dmjs, DMJ_SPI_CMD_SPI_WRITE)) {
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/* TODO: do SPI_WRITE */
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} else {
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/* TODO: do SPIOP */
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}
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}
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/* should only be called if it already has the cmd anyway (cf. spi_controller->flags) */
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static int dmj_spi_do_rdwr(struct dmj_spi *dmjs, void *rdata, const void *wdata, size_t len);
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static int dmj_spi_prepare_message(struct spi_controller *spictl, struct spi_message *msg)
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{
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struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
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struct spi_device *spidev = message->spi;
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struct device *dev = &spidev->dev;
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int ret;
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ret = dmj_spi_set_flags(dmjs, spidev->chip_select, kernmode_to_flags(spidev->mode));
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if (ret < 0) {
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dev_err(dev, "Failed to set SPI flags\n");
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return ret;
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}
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/*ret = dmj_spi_csmask_set_one(dmjs, spidev->chip_select);
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if (ret < 0) {
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dev_err(dev, "Failed to set CS mask\n");
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return ret;
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}*/
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return ret;
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}
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static int dmj_spi_set_cs(struct spi_device *spidev, bool enable)
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{
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struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
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struct spi_device *spidev = message->spi;
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struct device *dev = &spidev->dev;
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int ret;
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ret = dmj_spi_csmask_set_one(dmjs, spidev->chip_select);
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if (ret < 0) {
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dev_err(dev, "Failed to set CS mask\n");
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return ret;
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}
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ret = dmj_spi_cs_set(dmjs, spidev->chip_select, enable);
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if (ret < 0) {
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dev_err(dev, "Failed to set chip select line\n");
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return ret;
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}
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return 0;
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}
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static int dmj_spi_transfer_one(struct spi_controller *spictl, struct spi_device *spidev, struct spi_transfer *xfer)
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{
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struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
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struct device *dev = &spidev->dev;
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int ret;
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uint32_t cksize, todo, off = 0;
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ret = dmj_spi_set_freq(dmjs, spidev->chip_select, xfer->speed_hz);
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if (ret < 0) {
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dev_err(dev, "Failed to set SPI frequency to %d Hz\n", xfer->speed_hz);
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return ret;
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}
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ret = dmj_spi_set_bpw(dmjs, spidev->chip_select, xfer->bpw);
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if (ret < 0) {
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dev_err(dev, "Failed to set SPI bits-per-word to %d\n", xfer->bits_per_word);
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return ret;
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}
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cksize;
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if (xfer->tx_buf && xfer->rx_buf) {
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cksize = dmjs->wrnmaxlen;
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if (cksize > dmjs->rdnmaxlen) cksize = dmjs->rdnmaxlen;
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} else if (xfer->tx_buf) {
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cksize = dmjs->wrnmaxlen;
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} else if (xfer->rx_buf) {
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cksize = dmjs->rdnmaxlen;
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} else return -EINVAL;
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todo = xfer->len;
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do {
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if (todo < cksize) cksize = todo;
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if (xfer->tx_buf && xfer->rx_buf) {
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ret = dmj_spi_do_rdwr(dmjs, xfer->rx_buf + off, xfer->tx_buf + off, cksize);
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} else if (xfer->tx_buf) {
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ret = dmj_spi_do_write(dmjs, xfer->tx_buf + off, cksize);
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} else /*if (xfer->rx_buf)*/ {
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ret = dmj_spi_do_read(dmjs, xfer->rx_Buf + off, cksize);
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}
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if (ret < 0) return ret;
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todo -= cksize;
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off += cksize;
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} while (todo);
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return 0;
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}
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static int dmj_spi_probe(struct platform_device *pdev)
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{
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struct spi_controller *spictl;
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struct dmj_spi *dmjs;
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struct device *dev = &pdev->dev;
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int ret;
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controller = spi_alloc_controller(dev, sizeof(*dmjs));
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if (!controller) return -ENOMEM;
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platform_set_drvdata(pdev, controller);
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dmjs = spi_controller_get_devdata(spictl);
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dmjs->spictl = spictl;
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dmjs->spictl->dev.of_node = dev->of_node;
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dmjs->pdev = pdev;
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dmjs->csmask = 0xff;
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for (i = 0; i < 8; ++i) {
|
||||
dmjs->devsettings[i].freq = 0;
|
||||
dmjs->devsettings[i].flags = 0xff;
|
||||
dmjs->devsettings[i].bpw = 0xff;
|
||||
}
|
||||
|
||||
spin_lock_init(&dmjs->csmap_lock);
|
||||
|
||||
ret = dmj_spi_check_hw(dmjs);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Hardware capabilities lacking\n");
|
||||
goto err_free_ctl;
|
||||
}
|
||||
|
||||
ret = dmj_spi_get_caps(dmjs);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to get device capabilities\n");
|
||||
goto err_free_ctl;
|
||||
}
|
||||
|
||||
spictl->min_speed_hz = dmjs->caps.freq_min;
|
||||
spictl->max_speed_hz = dmjs->caps.freq_max;
|
||||
spictl->bits_per_word_mask = SPI_BPW_RANGE_MASK(dmjs->caps.min_bpw, dmjs->caps.max_bpw);
|
||||
spictl->num_chipselect = dmjs->caps.num_cs;
|
||||
spictl->mode_bits = devcaps_to_kernmode(dmjs->caps.flgcaps);
|
||||
|
||||
spictl->bus_num = -1;
|
||||
spictl->prepare_message = dmj_spi_prepare_message;
|
||||
spictl->transfer_one = dmj_spi_transfer_one;
|
||||
spictl->set_cs = dmj_spi_set_cs;
|
||||
|
||||
spictl->flags = 0;
|
||||
if (!has_cmd(dmjs, DMJ_SPI_CMD_SPI_RDWR))
|
||||
spictl->flags |= SPI_CONTROLLER_HALF_DUPLEX;
|
||||
|
||||
pm_runtime_set_autosuspend_delay(dev, DMJ_RPM_AUTOSUSPEND_TIMEOUT);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
pm_runtime_set_active(dev);
|
||||
pm_runtime_set_enable(dev);
|
||||
|
||||
ret = devm_spi_register_controller(dev, spictl);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to register SPI controller\n");
|
||||
goto err_dereg;
|
||||
}
|
||||
|
||||
return dmj_spi_set_pinstate(dmjs, true);
|
||||
|
||||
err_dereg:
|
||||
pm_runtime_disable(dev);
|
||||
pm_runtime_set_suspended(dev);
|
||||
err_free_ctl:
|
||||
spi_controller_put(spictl);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dmj_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *spictl = platform_get_drvdata(pdev);
|
||||
struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
dmj_spi_set_pinstate(dmjs, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int dmj_spi_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_controller *spictl = dev_get_drvdata(dev);
|
||||
struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
|
||||
int ret, i;
|
||||
|
||||
ret = spi_controller_suspend(spictl);
|
||||
if (ret < 0) return ret;
|
||||
|
||||
dmj_spi_set_pinstate(dmjs, false);
|
||||
|
||||
for (i = 0; i < 8; ++i) {
|
||||
dmjs->devsettings[i].freq = 0;
|
||||
dmjs->devsettings[i].flags = 0xff;
|
||||
dmjs->devsettings[i].bpw = 0xff;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dmj_spi_resume(struct device *dev)
|
||||
{
|
||||
struct spi_controller *spictl = dev_get_drvdata(dev);
|
||||
struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
|
||||
|
||||
dmj_spi_set_pinstate(dmjs, true);
|
||||
|
||||
return spi_controller_resume(spictl);
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int dmj_spi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_controller *spictl = dev_get_drvdata(dev);
|
||||
struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
|
||||
|
||||
return dmj_spi_set_pinstate(dmjs, false);
|
||||
}
|
||||
static int dmj_spi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct spi_controller *spictl = dev_get_drvdata(dev);
|
||||
struct dmj_spi *dmjs = spi_controller_get_devdata(spictl);
|
||||
|
||||
return dmj_spi_set_pinstate(dmjs, true);
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static const struct dev_pm_ops dmj_spi_pm = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(dmj_spi_suspend, dmj_spi_resume)
|
||||
SET_RUNTIME_PM_OPS(dmj_spi_runtime_suspend, dmj_spi_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver spi_dmj_driver = {
|
||||
.driver = {
|
||||
.name = "dmj-spi",
|
||||
.pm = &dmj_spi_pm,
|
||||
},
|
||||
.probe = dmj_spi_probe,
|
||||
.remove = dmj_spi_remove
|
||||
};
|
||||
module_platform_driver(spi_dmj_driver);
|
||||
|
||||
MODULE_AUTHOR("sys64738 <sys64738@disroot.org>");
|
||||
MODULE_AUTHOR("haskal <haskal@awoo.systems>");
|
||||
MODULE_DESCRIPTION("SPI interface driver for the " HARDWARE_NAME " USB multitool");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:dmj-spi");
|
||||
|
|
@ -71,6 +71,41 @@ enum serprog_caps {
|
|||
|
||||
#define SERPROG_IFACE_VERSION 0x0001
|
||||
|
||||
/*
|
||||
It’s easy to be confused here, and the vendor documentation you’ll find isn’t
|
||||
necessarily helpful. The four modes combine two mode bits:
|
||||
|
||||
CPOL indicates the initial clock polarity. CPOL=0 means the clock
|
||||
starts low, so the first (leading) edge is rising, and the second
|
||||
(trailing) edge is falling. CPOL=1 means the clock starts high, so the
|
||||
first (leading) edge is falling.
|
||||
|
||||
CPHA indicates the clock phase used to sample data; CPHA=0 says sample
|
||||
on the leading edge, CPHA=1 means the trailing edge.
|
||||
|
||||
Since the signal needs to stablize before it’s sampled, CPHA=0 implies
|
||||
that its data is written half a clock before the first clock edge. The
|
||||
chipselect may have made it become available.
|
||||
|
||||
Chip specs won’t always say “uses SPI mode X” in as many words, but their
|
||||
timing diagrams will make the CPOL and CPHA modes clear.
|
||||
|
||||
In the SPI mode number, CPOL is the high order bit and CPHA is the low order
|
||||
bit. So when a chip’s timing diagram shows the clock starting low (CPOL=0) and
|
||||
data stabilized for sampling during the trailing clock edge (CPHA=1), that’s
|
||||
SPI mode 1.
|
||||
|
||||
Note that the clock mode is relevant as soon as the chipselect goes active. So
|
||||
the master must set the clock to inactive before selecting a slave, and the
|
||||
slave can tell the chosen polarity by sampling the clock level when its select
|
||||
line goes active. That’s why many devices support for example both modes 0 and
|
||||
3: they don’t care about polarity, and always clock data in/out on rising clock
|
||||
edges.
|
||||
|
||||
|
||||
- Linux kernel docs
|
||||
*/
|
||||
|
||||
#ifdef DBOARD_HAS_SPI
|
||||
/* functions to be implemented by the BSP */
|
||||
uint32_t /*freq_applied*/ sp_spi_set_freq(uint32_t freq_wanted);
|
||||
|
|
|
|||
Loading…
Reference in New Issue