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SBW: fix TCLK bullshit

This commit is contained in:
Triss 2022-07-24 01:40:24 +02:00
parent c7ec7a1752
commit 61b8b97263
2 changed files with 9 additions and 9 deletions
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16
bsp/rp2040/m_isp/sbw.pio
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@ -86,18 +86,18 @@ PUBLIC sbw_tms_seq:
; alternatively, one could set the "load-bearing instruction" to a
; "set pins, 0/1 side 1 [12]" for a fixed value useful for single sets/clears
PUBLIC sbw_tclk_burst:
set pindirs, 1 side 1 ; SBWTDIO is now output
set pindirs, 1 side 1 ; SBWTDIO is now output
; tms slot:
set pins, 0 side 1 ; stay in run-test/idle TAP state
nop side 0 ; target reads TMS at falling edge
mov pins, y side 0 ; during low phase, prepare TCLK
set pins, 0 side 1 ; stay in run-test/idle TAP state
nop side 0 ; target reads TMS at falling edge
mov pins, y side 0 ; during low phase, prepare TCLK
; tdi slot:
nop side 1 [12] ; wait a bit
nop side 1 [6] ; wait a bit
burst_loop:
;PUBLIC sbw_tclk_burst_loadbearing_insn:
out pins, 1 side 1 [12] ; in the middle of TDI hiphase: do TCLK
jmp x--, burst_loop side 1 [12]
nop side 0 [1] ; need a low clock edge for TDO
out pins, 1 side 1 [6] ; in the middle of TDI hiphase: do TCLK
jmp x--, burst_loop side 1 [6]
nop side 0 [1] ; need a low clock edge for TDO
; tdo slot:
set pindirs, 0 side 1 [1]
nop side 0 [1]

2
bsp/rp2040/m_isp/sbw_hw.c
View File

@ -300,7 +300,7 @@ void sbw_clrset_tclk(bool value) {
void sbw_tclk_burst(uint32_t ncyc) {
//sbw_pio_loadbearing_set_outpins(PINOUT_SBW_PIO);
uint32_t txremain = ((ncyc + 7) >> 3) * 2;
uint32_t txremain = ((ncyc + 7) >> 3) * 2 - 1;
// MSB-first
uint8_t pattern = last_tclk ? 0x55 : 0xaa;