483 lines
20 KiB
C
483 lines
20 KiB
C
// vim: set et:
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#include "tusb_config.h"
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#include <tusb.h>
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#include "thread.h"
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#include "m_ftdi/bsp-feature.h"
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#include "m_ftdi/ftdi.h"
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// index = interface number (A/B)
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// out/in bRequest wValue wIndex data wLength
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// RESET: out 0 0 index
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// TCIFLUSH: out 0 2 index
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// TCOFLUSH: out 0 1 index
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// SETMODEMCTRL:out 1 (mask:8<<8 | data:8) // bit0=dtr bit1=rts
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// SETFLOWCTRL: out 2 xon?1:0 (flowctrl | index) // flowctrl: 0=disable, 1=ctsrts, 2=dtrdsr 4=xonxoff FROM VALUE, not set/reset!
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// SETBAUDRATE: out 3 brate brate24|index // 48 MHz clocks, /16? , baudrate is 24bit, highest byte in index MSB
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// SETLINEPROP: out 4 (break:1<<14 | stop:2<<11 | parity:3<<8 | bits:8) ; break: off/on, stop=1/15/2, parity=none/odd/even/mark/space; bits=7/8
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// POLLMODEMSTAT:in 5 0 index &modemstat len=2 // first byte: bit0..3=0 bit4=cts bit5=dts bit6=ri bit7=rlsd ; second byte: bit0=dr bit1=oe bit2=pe bit3=fe bit4=bi bit5=thre bit6=temt bit7=fifoerr
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// SETEVENTCHAR:out 6 (endis:1<<8 | char)
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// SETERRORCHAR:out 7 (endir:1<<8 | char)
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// <there is no bReqest 8>
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// SETLATENCY: out 9 latency(1..255)
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// GETLATENCY: in 0xa 0 index &latency len=1
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// SETBITBANG: out 0xb dirmask:8<<8 | mode:8 // mode: MPSSE mode: 0=serial/fifo, 1=bitbang, 2=mpsse, 4=syncbb, 8=mcu, 16=opto
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// READPINS: in 0xc 0 index &pins len=1
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// READEEPROM: in 0x90 0 eepaddr &val 2 // eepaddr in 16-bit units(?)
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// WRITEEEPROM: out 0x91 value eepaddr
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// ERASEEEPROM: out 0x92 0 0
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// eeprom layout:
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// max size is 128 words (256 bytes), little-endian
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// 00: type, driver, .. stuff (chanA byte, chanB byte) -> TODO: what does this mean exactly?
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// 0=UART 1=FIFO 2=opto 4=CPUFIFO 8=FT1284
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// 01: VID
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// 02: PID
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// 03: bcdDevice
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// 04: byte08: flags: bit7=1 bit6=1=selfpowered bit5=1=remotewakeup ; byte09=max power, 2mA units
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// 05: bit0=epin isochr, bit1=epout isochr, bit2=suspend pulldn, bit3=serialno use, bit4=usbver change, bit5..7=0
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// 06: bcdUSB
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// 07: byte0E=manufstr.off-0x80, byte0F=manufstr.len (in bytes, but 16-bit ascii)
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// 08: ^ but product
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// 09: ^ but serial
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// 0a: chip type (66 etc -> we emulate '00', internal)
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// "strings start at 0x96 for ft2232c" (byte addr)
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// checksum:
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// initial: 0xaaaa
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// digest 1 byte:
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// checksum = (checksum ^ word) <<< 1;
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// placed at last word of EEPROM
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// ftdi_write_data(), ftdi_read_data(): bulk xfer
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// input/tristate: 200K pullup
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// SI/WU: let's ignore this
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// UART mode: standard stuff
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// FIFO mode: RDF#=0: enable output. RD# rising when RXF#=0: fetch next byte
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// TXF#=0: enable input. WR falling when TXF#=0: write byte
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// bitbang mode: ^ similar, no RDF#/TXF#, RD#/WR# (now WR# jenai WR) pos depends on UART mode std (UART vs FIFO)
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// sync bitbang: doesn't use RD#/WR#, clocked by baudrate control
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// MPSSE: lots of magic. TCK/SK, TDI/DO, TDO/DI, TMS/CS, GPIOL0..3, GPIOH0..3(7?)
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// bulk xfer formats: (interface index <-> bulk epno)
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// * UART: ok I guess
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// * FIFO: same
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// * bitbang, sync bitbang: ???? (just data or also clock stuff?? ?)
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// * MPSSE, MCU: see separate PDF
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// * CPUFIFIO: same as FIFO ig
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// * opto, FT1284: not supported
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#ifdef DBOARD_HAS_FTDI
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int __builtin_ctz(unsigned int v);
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uint16_t ftdi_eeprom[128];
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void ftdi_init(void) {
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// init eeprom defaults
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memset(ftdi_eeprom, 0xff, sizeof ftdi_eeprom);
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ftdi_eeprom[ 0] = 0x0000; // both default to UART
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ftdi_eeprom[ 1] = 0x0403; // idVendor
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ftdi_eeprom[ 2] = 0x6010; // idProduct
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ftdi_eeprom[ 3] = 0x0500; // bcdDevice
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ftdi_eeprom[ 4] = 0x5080; // 100 mA, no flags
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ftdi_eeprom[ 5] = 0x0000; // more flags
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ftdi_eeprom[ 6] = 0x0110; // bcdUSB
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ftdi_eeprom[ 7] = 0x0000; // no manuf. str (TODO?)
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ftdi_eeprom[ 8] = 0x0000; // no prod. str (TODO?)
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ftdi_eeprom[ 9] = 0x0000; // no serial str (TODO?)
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ftdi_eeprom[10] = 0x0000; // internal chip
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ftdi_eeprom[0x7f] = ftdi_eeprom_checksum_calc(ftdi_eeprom, 0x7f);
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memset(&ftdi_ifa, 0, sizeof ftdi_ifa);
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memset(&ftdi_ifb, 0, sizeof ftdi_ifb);
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ftdi_ifa.lineprop = sio_bits_8 | sio_stop_1; // 8n1
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ftdi_ifb.lineprop = sio_bits_8 | sio_stop_1; // 8n1
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ftdi_ifa.index = 0;
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ftdi_ifb.index = 1;
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ftdi_if_init(&ftdi_ifa);
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ftdi_if_init(&ftdi_ifb);
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}
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void ftdi_deinit(void) {
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ftdi_if_deinit(&ftdi_ifa);
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ftdi_if_deinit(&ftdi_ifb);
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}
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static uint8_t vnd_read_byte(struct ftdi_interface* itf, int itfnum) {
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while (itf->rxavail <= 0) {
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if (!tud_vendor_n_mounted(itfnum) || !tud_vendor_n_available(itfnum)) {
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thread_yield();
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continue;
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}
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itf->rxpos = 0;
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itf->rxavail = tud_vendor_n_read(itfnum, itf->bufbuf, sizeof itf->bufbuf);
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if (itf->rxavail == 0) thread_yield();
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}
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uint8_t rv = itf->bufbuf[itf->rxpos];
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++itf->rxpos;
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--itf->rxavail;
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return rv;
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}
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typedef void (*ftfifo_write_fn)(struct ftdi_interface*, const uint8_t*, size_t);
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typedef size_t (*ftfifo_read_fn)(struct ftdi_interface*, uint8_t*, size_t);
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struct ftfifo_fns {
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ftfifo_write_fn write;
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ftfifo_read_fn read ;
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};
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static const struct ftfifo_fns fifocbs[] = {
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{ ftdi_if_uart_write, ftdi_if_uart_read }, // technically mpsse
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{ ftdi_if_asyncbb_write, ftdi_if_asyncbb_read },
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{ ftdi_if_syncbb_write, ftdi_if_syncbb_read },
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{ NULL, NULL }, // mcuhost
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{ ftdi_if_fifo_write, ftdi_if_fifo_read },
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{ NULL, NULL }, // opto
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{ ftdi_if_cpufifo_write, ftdi_if_cpufifo_read },
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{ NULL, NULL }, // ft1284
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};
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// for handling USB bulk commands
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static void ftdi_task(int itfnum) {
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if (!tud_vendor_n_mounted(itfnum)) return; // can't do much in this case
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struct ftdi_interface* itf;
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if (itfnum == VND_N_FTDI_IFA) itf = &ftdi_ifa;
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else if (itfnum == VND_N_FTDI_IFB) itf = &ftdi_ifb;
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else return;
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// for UART, FIFO, asyncbb, syncbb, and CPUfifo modes, operation is
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// relatively straightforward: the device acts like some sort of FIFO, so
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// it's just shoving bytes to the output pins. MPSSE and MCU host emulation
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// modes are more difficult, as the bulk data actually has some form of
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// protocol.
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enum ftdi_mode mode = ftdi_if_get_mode(itf);
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struct ftfifo_fns fifocb = fifocbs[(mode == 0) ? 0 : __builtin_ctz(mode)];
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uint32_t avail;
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uint8_t cmdbyte = 0;
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switch (mode) {
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case ftmode_uart : case ftmode_fifo : case ftmode_cpufifo:
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case ftmode_asyncbb: case ftmode_syncbb:
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if (fifocb.read == NULL || fifocb.write == NULL) goto CASE_DEFAULT; // welp
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avail = tud_vendor_n_available(itfnum);
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if (avail) {
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tud_vendor_n_read(itfnum, itf->writebuf, avail);
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fifocb.write(itf, itf->writebuf, avail);
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}
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do {
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avail = fifocb.read(itf, itf->readbuf, sizeof itf->readbuf);
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if (avail) tud_vendor_n_write(itfnum, itf->readbuf, avail);
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} while (avail == sizeof itf->readbuf);
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break;
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case ftmode_mpsse:
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avail = 0;
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switch ((cmdbyte = vnd_read_byte(itf, itfnum))) {
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case ftmpsse_set_dirval_lo: // low byte of output gpio, not to low level
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itf->writebuf[0] = vnd_read_byte(itf, itfnum); // val
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itf->writebuf[1] = vnd_read_byte(itf, itfnum); // dir
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ftdi_if_mpsse_set_dirval_lo(itf, itf->writebuf[1], itf->writebuf[0]);
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break;
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case ftmpsse_set_dirval_hi:
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itf->writebuf[0] = vnd_read_byte(itf, itfnum); // val
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itf->writebuf[1] = vnd_read_byte(itf, itfnum); // dir
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ftdi_if_mpsse_set_dirval_hi(itf, itf->writebuf[1], itf->writebuf[0]);
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break;
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case ftmpsse_read_lo:
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itf->readbuf[0] = ftdi_if_mpsse_read_lo(itf);
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avail = 1;
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break;
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case ftmpsse_read_hi:
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itf->readbuf[0] = ftdi_if_mpsse_read_hi(itf);
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avail = 1;
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break;
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case ftmpsse_loopback_on : ftdi_if_mpsse_loopback(itf, true ); break;
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case ftmpsse_loopback_off: ftdi_if_mpsse_loopback(itf, false); break;
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case ftmpsse_set_clkdiv:
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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ftdi_if_mpsse_set_clkdiv(itf, (uint16_t)avail);
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avail = 0;
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break;
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case ftmpsse_flush: ftdi_if_mpsse_flush(itf); break;
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case ftmpsse_wait_io_hi: ftdi_if_mpsse_wait_io(itf, true ); break;
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case ftmpsse_wait_io_lo: ftdi_if_mpsse_wait_io(itf, false); break;
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case ftmpsse_div5_disable: ftdi_if_mpsse_div5(itf, false); break;
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case ftmpsse_div5_enable : ftdi_if_mpsse_div5(itf, true ); break;
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case ftmpsse_data_3ph_en : ftdi_if_mpsse_data_3ph(itf, true ); break;
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case ftmpsse_data_3ph_dis: ftdi_if_mpsse_data_3ph(itf, false); break;
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case ftmpsse_clockonly_bits: ftdi_if_mpsse_clockonly(itf, vnd_read_byte(itf, itfnum)); break;
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case ftmpsse_clockonly_bytes:
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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ftdi_if_mpsse_clockonly(itf, avail);
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avail = 0;
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break;
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case ftmpsse_clock_wait_io_hi: ftdi_if_mpsse_clock_wait_io(itf, true ); break;
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case ftmpsse_clock_wait_io_lo: ftdi_if_mpsse_clock_wait_io(itf, false); break;
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case ftmpsse_adapclk_enable : ftdi_if_mpsse_adaptive(itf, true ); break;
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case ftmpsse_adapclk_disable: ftdi_if_mpsse_adaptive(itf, false); break;
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case ftmpsse_clock_bits_wait_io_hi:
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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ftdi_if_mpsse_clockonly_wait_io(itf, true, avail);
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avail = 0;
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break;
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case ftmpsse_clock_bits_wait_io_lo:
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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ftdi_if_mpsse_clockonly_wait_io(itf, false, avail);
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avail = 0;
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break;
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case ftmpsse_hi_is_tristate:
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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ftdi_if_mpsse_hi_is_tristate(itf, avail);
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avail = 0;
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break;
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default: CASE_DEFAULT:
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if (!(cmdbyte & ftmpsse_specialcmd)) {
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if (cmdbyte & ftmpsse_tmswrite) {
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if (cmdbyte & ftmpsse_bitmode) {
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itf->writebuf[0] = vnd_read_byte(itf, itfnum); // number of bits
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itf->writebuf[1] = vnd_read_byte(itf, itfnum); // data bits to output
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itf->readbuf[0] = ftdi_if_mpsse_tms_xfer(itf, cmdbyte, itf->writebuf[0], itf->writebuf[1]);
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if (cmdbyte & ftmpsse_tdoread) avail = 1;
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break;
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}
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// else: fallthru to error code
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} else {
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if (cmdbyte & ftmpsse_bitmode) {
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itf->writebuf[0] = vnd_read_byte(itf, itfnum); // number of bits
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if (cmdbyte & ftmpsse_tdiwrite)
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itf->writebuf[1] = vnd_read_byte(itf, itfnum); // data bits to output
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itf->readbuf[0] = ftdi_if_mpsse_xfer_bits(itf, cmdbyte, itf->writebuf[0], itf->writebuf[1]);
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if (cmdbyte & ftmpsse_tdoread) avail = 1;
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break;
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} else {
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avail = vnd_read_byte(itf, itfnum);
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avail |= (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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for (size_t i = 0; i < avail; i += 64) {
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uint32_t thisbatch = avail - i;
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if (thisbatch > 64) thisbatch = 64;
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for (size_t j = 0; j < thisbatch; ++j)
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itf->writebuf[j] = vnd_read_byte(itf, itfnum);
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ftdi_if_mpsse_xfer_bytes(itf, cmdbyte, thisbatch, itf->readbuf, itf->writebuf);
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tud_vendor_n_write(itfnum, itf->readbuf, thisbatch);
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}
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avail = 0;
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break;
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}
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}
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}
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itf->readbuf[0] = 0xfa;
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itf->readbuf[1] = cmdbyte;
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avail = 2;
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break;
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}
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if (avail) tud_vendor_n_write(itfnum, itf->readbuf, avail);
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break;
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case ftmode_mcuhost:
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avail = 0;
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switch ((cmdbyte = vnd_read_byte(itf, itfnum))) {
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case ftmcu_flush: ftdi_if_mcuhost_flush(itf); break;
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case ftmcu_wait_io_hi: ftdi_if_mcuhost_wait_io(itf, true ); break;
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case ftmcu_wait_io_lo: ftdi_if_mcuhost_wait_io(itf, false); break;
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case ftmcu_read8:
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itf->readbuf[0] = ftdi_if_mcuhost_read8(itf, vnd_read_byte(itf, itfnum));
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avail = 1;
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break;
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case ftmcu_read16:
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avail = (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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avail |= vnd_read_byte(itf, itfnum);
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itf->readbuf[0] = ftdi_if_mcuhost_read16(itf, (uint16_t)avail);
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avail = 1;
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break;
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case ftmcu_write8:
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itf->writebuf[0] = vnd_read_byte(itf, itfnum);
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itf->writebuf[1] = vnd_read_byte(itf, itfnum);
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ftdi_if_mcuhost_write8(itf, itf->writebuf[0], itf->writebuf[1]);
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break;
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case ftmcu_write16:
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avail = (uint32_t)vnd_read_byte(itf, itfnum) << 8;
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avail |= vnd_read_byte(itf, itfnum);
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itf->writebuf[0] = vnd_read_byte(itf, itfnum);
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ftdi_if_mcuhost_write8(itf, avail, itf->writebuf[0]);
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avail = 0;
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break;
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default: // send error response when command doesn't exist
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itf->readbuf[0] = 0xfa;
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itf->readbuf[1] = cmdbyte;
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avail = 2;
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break;
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}
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if (avail) tud_vendor_n_write(itfnum, itf->readbuf, avail);
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break;
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default: // drop incoming data so that the pipes don't get clogged. can't do much else
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avail = tud_vendor_n_available(itfnum);
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if (avail) tud_vendor_n_read(itfnum, itf->writebuf, avail);
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break;
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}
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}
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void ftdi_task_ifa(void) { ftdi_task(VND_N_FTDI_IFA); }
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void ftdi_task_ifb(void) { ftdi_task(VND_N_FTDI_IFB); }
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#define FT2232D_CLOCK (48*1000*1000)
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uint32_t ftdi_if_decode_baudrate(uint32_t enc_brate) { // basically reversing libftdi ftdi_to_clkbits
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static const uint8_t ftdi_brate_frac_lut[8] = { 0, 4, 2, 1, 3, 5, 6, 7 };
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// special cases
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if (enc_brate == 0) return FT2232D_CLOCK >> 4;
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else if (enc_brate == 1) return FT2232D_CLOCK / 24;
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else if (enc_brate == 2) return FT2232D_CLOCK >> 5;
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uint32_t div = (enc_brate & 0x7fff) << 3; // integer part
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div = div | ftdi_brate_frac_lut[(enc_brate >> 14) & 7];
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uint32_t baud = FT2232D_CLOCK / div;
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if (baud & 1) baud = (baud >> 1) + 1; // raunding
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else baud >>= 1;
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return baud;
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}
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static uint8_t control_buf[2];
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bool ftdi_control_xfer_cb(uint8_t rhport, uint8_t stage,
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tusb_control_request_t const* req) {
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// return true: don't stall
|
|
// return false: stall
|
|
|
|
// not a vendor request -> not meant for this code
|
|
if (req->bmRequestType_bit.type != TUSB_REQ_TYPE_VENDOR) return true;
|
|
|
|
// data stage not needed: data stages only for device->host xfers, never host->device
|
|
if (stage != CONTROL_STAGE_SETUP) return true;
|
|
|
|
// tud_control_status(rhport, req); : acknowledge
|
|
// tud_control_xfer(rhport, req, bufaddr, size); : ack + there's a data phase with stuff to do
|
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// write: send bufaddr value. read: data stage will have bufaddr filled out
|
|
|
|
// do EEPROM stuff first, as these don't use wIndex as channel select
|
|
uint16_t tmp16;
|
|
switch (req->bRequest) {
|
|
case sio_readeeprom:
|
|
tmp16 = ftdi_eeprom[req->wIndex & 0x7f];
|
|
control_buf[0] = tmp16 & 0xff;
|
|
control_buf[1] = tmp16 >> 8;
|
|
return tud_control_xfer(rhport, req, control_buf, 2);
|
|
case sio_writeeeprom:
|
|
ftdi_eeprom[req->wIndex & 0x7f] = req->wValue;
|
|
return tud_control_status(rhport, req);
|
|
case sio_eraseeeprom:
|
|
memset(ftdi_eeprom, 0xff, sizeof ftdi_eeprom);
|
|
return tud_control_status(rhport, req);
|
|
}
|
|
|
|
int itfnum = req->wIndex & 0xff;
|
|
struct ftdi_interface* itf = &ftdi_ifa; // default
|
|
|
|
if (itfnum > 2) return false; // bad interface number
|
|
else if (itfnum == 1) itf = &ftdi_ifa;
|
|
else if (itfnum == 2) itf = &ftdi_ifb;
|
|
|
|
switch (req->bRequest) {
|
|
case sio_cmd:
|
|
if (req->wValue == sio_reset) {
|
|
itf->modem_mask = 0;
|
|
itf->modem_data = 0;
|
|
itf->flow = ftflow_none;
|
|
itf->lineprop = sio_bits_8 | sio_stop_1; // 8n1
|
|
itf->charen = 0;
|
|
itf->bb_dir = 0;
|
|
itf->bb_mode = sio_mode_reset;
|
|
itf->mcu_addr_latch = 0;
|
|
itf->rxavail = 0; itf->rxpos = 0;
|
|
ftdi_if_sio_reset(itf);
|
|
} else if (req->wValue == sio_tciflush) {
|
|
itf->rxavail = 0; itf->rxpos = 0;
|
|
ftdi_if_sio_tciflush(itf);
|
|
} else if (req->wValue == sio_tcoflush) {
|
|
// nothing extra to clear here I think
|
|
ftdi_if_sio_tcoflush(itf);
|
|
} else return false; // unk
|
|
return tud_control_status(rhport, req);
|
|
case sio_setmodemctrl:
|
|
ftdi_if_set_modemctrl(itf,
|
|
itf->modem_mask = (req->wValue >> 8),
|
|
itf->modem_data = (req->wValue & 0xff));
|
|
return tud_control_status(rhport, req);
|
|
case sio_setflowctrl: {
|
|
enum ftdi_flowctrl flow = (req->wIndex >> 8);
|
|
if (!req->wValue)
|
|
flow = (flow & ~ftflow_xonxoff) | (itf->flow & ftflow_xonxoff);
|
|
ftdi_if_set_flowctrl(itf, itf->flow = flow);
|
|
} return tud_control_status(rhport, req);
|
|
case sio_setbaudrate: {
|
|
uint32_t enc_brate = (uint32_t)req->wValue | ((uint32_t)(req->wIndex & 0xff00) << 8);
|
|
uint32_t brate = ftdi_if_decode_baudrate(enc_brate);
|
|
ftdi_if_set_baudrate(itf, itf->baudrate = brate);
|
|
} return tud_control_status(rhport, req);
|
|
case sio_setlineprop:
|
|
ftdi_if_set_lineprop(itf, itf->lineprop = req->wValue);
|
|
return tud_control_status(rhport, req);
|
|
case sio_pollmodemstat:
|
|
tmp16 = ftdi_if_poll_modemstat(itf);
|
|
control_buf[0] = tmp16 & 0xff;
|
|
control_buf[1] = tmp16 >> 8;
|
|
return tud_control_xfer(rhport, req, control_buf, 2);
|
|
case sio_seteventchar:
|
|
if (req->wValue >> 8) itf->charen |= eventchar_enable;
|
|
else if (itf->charen & eventchar_enable) itf->charen ^= eventchar_enable;
|
|
ftdi_if_set_eventchar(itf, req->wValue >> 8,
|
|
itf->eventchar = (req->wValue & 0xff));
|
|
return tud_control_status(rhport, req);
|
|
case sio_seterrorchar:
|
|
if (req->wValue >> 8) itf->charen |= errorchar_enable;
|
|
else if (itf->charen & errorchar_enable) itf->charen ^= errorchar_enable;
|
|
ftdi_if_set_errorchar(itf, req->wValue >> 8,
|
|
itf->errorchar = (req->wValue & 0xff));
|
|
return tud_control_status(rhport, req);
|
|
case sio_setlatency:
|
|
ftdi_if_set_latency(itf, itf->latency = (req->wValue & 0xff));
|
|
return tud_control_status(rhport, req);
|
|
case sio_getlatency:
|
|
control_buf[0] = ftdi_if_get_latency(itf);
|
|
return tud_control_xfer(rhport, req, control_buf, 1);
|
|
case sio_setbitbang: {
|
|
uint8_t olddir = itf->bb_dir;
|
|
enum ftdi_sio_bitmode oldmode = itf->bb_mode;
|
|
ftdi_if_set_bitbang(itf,
|
|
itf->bb_dir = (req->wValue >> 8),
|
|
itf->bb_mode = (req->wValue & 0xff),
|
|
olddir, oldmode);
|
|
} return tud_control_status(rhport, req);
|
|
case sio_readpins:
|
|
control_buf[0] = ftdi_if_read_pins(itf);
|
|
return tud_control_xfer(rhport, req, control_buf, 1);
|
|
default: return false; // stall if not recognised
|
|
}
|
|
}
|
|
|
|
#endif /* DBOARD_HAS_FTDI */
|
|
|