95 lines
3.4 KiB
Plaintext
95 lines
3.4 KiB
Plaintext
;
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; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;
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.program swo_uart_rx_mini
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; Minimum viable 8n1 UART receiver. Wait for the start bit, then sample 8 bits
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; with the correct timing.
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; IN pin 0 is mapped to the GPIO used as UART RX.
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; Autopush must be enabled, with a threshold of 8.
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wait 0 pin 0 ; Wait for start bit
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set x, 7 [10] ; Preload bit counter, delay until eye of first data bit
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bitloop: ; Loop 8 times
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in pins, 1 ; Sample data
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jmp x-- bitloop [6] ; Each iteration is 8 cycles
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% c-sdk {
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#include "hardware/clocks.h"
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#include "hardware/gpio.h"
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static inline void swo_uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
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pio_gpio_init(pio, pin);
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gpio_pull_up(pin);
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pio_sm_config c = swo_uart_rx_mini_program_get_default_config(offset);
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sm_config_set_in_pins(&c, pin); // for WAIT, IN
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// Shift to right, autopush enabled
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sm_config_set_in_shift(&c, true, true, 8);
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
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// SM transmits 1 bit per 8 execution cycles.
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float div = (float)clock_get_hz(clk_sys) / (8 * baud);
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sm_config_set_clkdiv(&c, div);
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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.program swo_uart_rx
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; Slightly more fleshed-out 8n1 UART receiver which handles framing errors and
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; break conditions more gracefully.
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; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX.
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start:
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wait 0 pin 0 ; Stall until start bit is asserted
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set x, 7 [10] ; Preload bit counter, then delay until halfway through
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bitloop: ; the first data bit (12 cycles incl wait, set).
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in pins, 1 ; Shift data bit into ISR
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jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles
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jmp pin good_stop ; Check stop bit (should be high)
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irq 4 rel ; Either a framing error or a break. Set a sticky flag,
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wait 1 pin 0 ; and wait for line to return to idle state.
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jmp start ; Don't push data if we didn't see good framing.
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good_stop: ; No delay before returning to start; a little slack is
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push ; important in case the TX clock is slightly too fast.
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% c-sdk {
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static inline void swo_uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
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pio_gpio_init(pio, pin);
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gpio_pull_up(pin);
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pio_sm_config c = swo_uart_rx_program_get_default_config(offset);
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sm_config_set_in_pins(&c, pin); // for WAIT, IN
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sm_config_set_jmp_pin(&c, pin); // for JMP
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// Shift to right, autopull disabled
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sm_config_set_in_shift(&c, true, false, 32);
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// Deeper FIFO as we're not doing any TX
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
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// SM transmits 1 bit per 8 execution cycles.
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float div = (float)clock_get_hz(clk_sys) / (8 * baud);
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sm_config_set_clkdiv(&c, div);
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pio_sm_init(pio, sm, offset, &c);
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//pio_sm_set_enabled(pio, sm, true);
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}
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static inline char swo_uart_rx_program_getc(PIO pio, uint sm) {
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// 8-bit read from the uppermost byte of the FIFO, as data is left-justified
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io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3;
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while (pio_sm_is_rx_fifo_empty(pio, sm))
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tight_loop_contents();
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return (char)*rxfifo_shift;
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}
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%}
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