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Update 'USB config & command protocol'

Triss 2021-07-15 02:18:53 +00:00
parent b203575419
commit c852f58231
1 changed files with 31 additions and 9 deletions
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USB-config-%26-command-protocol.md

@ -77,15 +77,37 @@ Supported standard serprog commands:
Additionally, a number of nonstandard commands are supported as well, for more specific SPI transfers not necessarily needed for flash programming:
* `S_CMD_Q_NUM_CS` (`0x40`): query the number of SPI devices (and chip select lines) available, single byte response.
* `S_CMD_S_SPI_FLAGS` (`0x41`): set SPI transfer options:
* `S_FLG_CPOL` (`0x01`): set this bit to set the SPI clock polarity to *high*, clear this bit to set it to *low*.
* `S_FLG_CPHA` (`0x02`): set this bit to set the SPI clock phase to read or write data on the second edge, clear it to read/write it on the first edge.
* `S_FLG_16BIT` (`0x03`): set this bit to transfer data in units of 16-bit, clear this to perform 8-bit transfers. Data is always sent MSB-first.
* Flags default to all-zero.
* `S_CMD_SPI_READ` (`0x42`): similar to `SPIOP` (`0x13`), except without data to write (and no "write data length" argument).
* `S_CMD_SPI_WRITE` (`0x43`): similar to `SPIOP` (`0x13`), except without data to read (and no "read data length" argument).
* `S_CMD_SPI_RDWR` (`0x44`): full-duplex SPI transfer (as opposed to `SPIOP` (`0x13`), which is only half-duplex), same arguments and result format as `SPIOP` (`0x13`).
* `S_CMD_Q_SPI_CAPS` (`0x40`): query capabilities of the SPI controller. No arguments. Return struct of 13 bytes (preceded by an `ACK`):
* Minimum frequency: 32-bit little-endian value in Hz
* Maximum frequency: 32-bit little-endian value in Hz
* Capability flags: 16-bit little-endian value
* Bit 0 (lsb): CPHA can be 1
* Bit 1: CPHA can be 0
* Bit 2: CPOL can be 1
* Bit 3: CPOL can be 0
* Bit 4: Standard SPI ("Motorola") frame format is supported
* Bit 5: TI SSP frame format is supported
* Bit 6: NatSemi MicroWire frame format is supported
* Bit 7: MSBit-first transfers are supported
* Bit 8: LSBit-first transfers are supported
* Bit 9: CS can be selected to be active-high instead (CS line control command will take note of this, and send CS high/low commands accordingly (in accordance with [https://elixir.bootlin.com/linux/latest/source/drivers/spi/spi.c#L818](the Linux kernel)), cf. `S_CMD_S_SPI_SETCS`.)
* Bit 10 (msb): 3-wire interface supported
* Number of chip-select lines: 8-bit bitmap
* Minimum bits-per-transfer-word value (8 bit)
* Maximum bits-per-transfer-word value (8 bit)
* `S_CMD_S_SPI_CHIPN` (`0x41`): set which chip select lines are to be controlled. Has a single argument byte, a bitmap of chip select line values.
* `S_CMD_S_SPI_SETCS` (`0x42`): set the voltage level of the CS line(s) selected by `S_CMD_S_SPI_CHIPN`.
* `S_CMD_S_SPI_FLAGS` (`0x43`): set transfer settings flags, single argument byte:
* Bit 0 (lsb): `CPHA`
* Bit 1: `CPOL`
* Bit 2,3: frame format: `0=standard`, `1=SSP`, `2=MicroWire`. 3 is undefined.
* Bit 4: LSBit-first transfer (clear this bit for MSBit-first transfers)
* Bit 5: CS is used as active-high signal (clear this bit for active-low CS signals)
* Bit 6 (msb): Use 3-wire mode (clear this bit for regular 4-wire SPI)
* `S_CMD_S_SPI_BPW` (`0x44`): set bits per word used in a SPI transfer. Single argument byte denoting the number of bits.
* `S_CMD_SPI_READ` (`0x45`): similar to `SPIOP` (`0x13`), except without data to write (and no "write data length" argument).
* `S_CMD_SPI_WRITE` (`0x46`): similar to `SPIOP` (`0x13`), except without data to read (and no "read data length" argument).
* `S_CMD_SPI_RDWR` (`0x47`): full-duplex SPI transfer (as opposed to `SPIOP` (`0x13`), which is only half-duplex), same arguments and result format as `SPIOP` (`0x13`).
#### I2C commands