ch32f1: Further formatting and layout cleanup
This commit is contained in:
dragonmux
Piotr Esden-Tempski
parent
fbc87cc518
commit
0368b76078
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@ -41,11 +41,11 @@ static int ch32f1_flash_write(struct target_flash *f,
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// these are common with stm32f1/gd32f1/...
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x04)
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#define FLASH_SR (FPEC_BASE+0x0C)
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#define FLASH_CR (FPEC_BASE+0x10)
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#define FLASH_AR (FPEC_BASE+0x14)
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#define FLASH_ACR (FPEC_BASE + 0x00)
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#define FLASH_KEYR (FPEC_BASE + 0x04)
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#define FLASH_SR (FPEC_BASE + 0x0C)
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#define FLASH_CR (FPEC_BASE + 0x10)
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#define FLASH_AR (FPEC_BASE + 0x14)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_SR_BSY (1 << 0)
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@ -57,14 +57,14 @@ static int ch32f1_flash_write(struct target_flash *f,
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#define FLASHSIZE 0x1FFFF7E0
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// these are specific to ch32f1
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#define FLASH_MAGIC (FPEC_BASE+0x34)
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#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x
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#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock
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#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program
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#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase
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#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load
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#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset
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#define FLASH_SR_EOP (1<<5) // End of programming
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#define FLASH_MAGIC (FPEC_BASE + 0x34)
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#define FLASH_MODEKEYR_CH32 (FPEC_BASE + 0x24) // Fast mode for CH32F10x
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#define FLASH_CR_FLOCK_CH32 (1 << 15) // fast unlock
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#define FLASH_CR_FTPG_CH32 (1 << 16) // fast page program
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#define FLASH_CR_FTER_CH32 (1 << 17) // fast page erase
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#define FLASH_CR_BUF_LOAD_CH32 (1 << 18) // Buffer load
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#define FLASH_CR_BUF_RESET_CH32 (1 << 19) // Buffer reset
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#define FLASH_SR_EOP (1 << 5) // End of programming
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#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
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/**
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@ -89,38 +89,41 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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target_add_flash(t, f);
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}
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#define WAIT_BUSY() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if(target_check_error(t)) { \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (sr & FLASH_SR_BSY);
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#define WAIT_BUSY() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if (target_check_error(t)) { \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (sr & FLASH_SR_BSY);
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#define WAIT_EOP() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if(target_check_error(t)) { \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (!(sr & FLASH_SR_EOP));
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#define WAIT_EOP() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if (target_check_error(t)) { \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (!(sr & FLASH_SR_EOP));
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#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP)
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#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP)
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#define SET_CR(bit) { ct = target_mem_read32(t, FLASH_CR); \
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ct |= (bit); \
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target_mem_write32(t, FLASH_CR, ct);}
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#define SET_CR(bit) do { \
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const uint32_t cr = target_mem_read32(t, FLASH_CR) | (bit); \
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target_mem_write32(t, FLASH_CR, cr); \
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} while(0)
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#define CLEAR_CR(bit) {ct = target_mem_read32(t, FLASH_CR); \
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ct &= ~(bit); \
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target_mem_write32(t, FLASH_CR, ct);}
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#define CLEAR_CR(bit) do { \
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const uint32_t cr = target_mem_read32(t, FLASH_CR) & (~(bit)); \
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target_mem_write32(t, FLASH_CR, cr); \
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} while(0)
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// Which one is the right value ?
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#define MAGIC_WORD 0x100
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// #define MAGIC_WORD 0x1000
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#define MAGIC(adr) { magic = target_mem_read32(t,(adr) ^ MAGIC_WORD); \
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target_mem_write32(t, FLASH_MAGIC , magic); }
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#define MAGIC(addr) do { \
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magic = target_mem_read32(t, (addr) ^ MAGIC_WORD); \
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target_mem_write32(t, FLASH_MAGIC , magic); \
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} while(0)
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/**
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\fn ch32f1_flash_unlock
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@ -130,11 +133,11 @@ static int ch32f1_flash_unlock(target *t)
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{
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DEBUG_INFO("CH32: flash unlock \n");
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target_mem_write32(t, FLASH_KEYR , KEY1);
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target_mem_write32(t, FLASH_KEYR , KEY2);
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target_mem_write32(t, FLASH_KEYR, KEY1);
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target_mem_write32(t, FLASH_KEYR, KEY2);
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// fast mode
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1);
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2);
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target_mem_write32(t, FLASH_MODEKEYR_CH32, KEY1);
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target_mem_write32(t, FLASH_MODEKEYR_CH32, KEY2);
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uint32_t cr = target_mem_read32(t, FLASH_CR);
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if (cr & FLASH_CR_FLOCK_CH32) {
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DEBUG_WARN("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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@ -145,7 +148,6 @@ static int ch32f1_flash_unlock(target *t)
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static int ch32f1_flash_lock(target *t)
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{
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volatile uint32_t ct;
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DEBUG_INFO("CH32: flash lock \n");
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SET_CR(FLASH_CR_LOCK);
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return 0;
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@ -177,13 +179,14 @@ bool ch32f1_probe(target *t)
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t->driver = "CH32F1 medium density (stm32f1 clone)";
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return true;
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}
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/**
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\fn ch32f1_flash_erase
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\brief fast erase of CH32
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*/
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int ch32f1_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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volatile uint32_t ct, sr, magic;
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volatile uint32_t sr, magic;
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target *t = f->t;
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DEBUG_INFO("CH32: flash erase \n");
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@ -244,7 +247,7 @@ static bool ch32f1_wait_flash_ready(target *t, uint32_t addr)
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static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t offset)
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{
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volatile uint32_t ct, sr, magic;
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volatile uint32_t sr, magic;
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const uint32_t *ss = (const uint32_t *)(src+offset);
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uint32_t dd = dest + offset;
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@ -266,7 +269,7 @@ static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t off
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*/
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int ch32f1_buffer_clear(target *t)
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{
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volatile uint32_t ct, sr;
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volatile uint32_t sr;
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SET_CR(FLASH_CR_FTPG_CH32); // Fast page program 4-
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SET_CR(FLASH_CR_BUF_RESET_CH32); // BUF_RESET 5-
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WAIT_BUSY(); // 6-
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@ -281,7 +284,7 @@ int ch32f1_buffer_clear(target *t)
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static int ch32f1_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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volatile uint32_t ct, sr, magic;
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volatile uint32_t sr, magic;
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target *t = f->t;
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size_t length = len;
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#ifdef CH32_VERIFY
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