Remove EXTENDED_RESET define
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a3c2592e44
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085c980215
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@ -444,7 +444,7 @@ static void cortexm_reset(target *t)
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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/* If target needs to do something extra (see Atmel SAM4L for example) */
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/* If target needs to do something extra (see Atmel SAM4L for example) */
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if ((t->target_options & CORTEXM_TOPT_EXTENDED_RESET) != 0) {
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if (t->extended_reset != NULL) {
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t->extended_reset(t);
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t->extended_reset(t);
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}
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}
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@ -155,7 +155,6 @@
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#define ARM_THUMB_BREAKPOINT 0xBE00
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#define ARM_THUMB_BREAKPOINT 0xBE00
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#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
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#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
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#define CORTEXM_TOPT_EXTENDED_RESET (1 << 3)
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bool cortexm_probe(ADIv5_AP_t *ap);
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bool cortexm_probe(ADIv5_AP_t *ap);
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ADIv5_AP_t *cortexm_ap(target *t);
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ADIv5_AP_t *cortexm_ap(target *t);
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@ -229,12 +229,7 @@ bool sam4l_probe(target *t)
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t->idcode = target_mem_read32(t, SAM4L_CHIPID_CIDR);
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t->idcode = target_mem_read32(t, SAM4L_CHIPID_CIDR);
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if (((t->idcode >> CHIPID_CIDR_ARCH_SHIFT) & CHIPID_CIDR_ARCH_MASK) == SAM4L_ARCH) {
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if (((t->idcode >> CHIPID_CIDR_ARCH_SHIFT) & CHIPID_CIDR_ARCH_MASK) == SAM4L_ARCH) {
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t->driver = "Atmel SAM4L";
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t->driver = "Atmel SAM4L";
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#ifdef SAM4_DISABLE_SRST
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/* this function says we need to do "extra" stuff after reset */
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/* Check to see if our extended reset will fix this */
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t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
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#endif
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/* this option says we need to do "extra" stuff after reset */
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t->target_options |= CORTEXM_TOPT_EXTENDED_RESET;
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t->extended_reset = sam4l_extended_reset;
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t->extended_reset = sam4l_extended_reset;
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ram_size = sam_ram_size(t->idcode);
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ram_size = sam_ram_size(t->idcode);
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target_add_ram(t, 0x20000000, ram_size);
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target_add_ram(t, 0x20000000, ram_size);
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