ch32f1: formatting cleanup to bring things closer to inline with the rest of the codebase
This commit is contained in:
dragonmux
Piotr Esden-Tempski
parent
9aba7ecce2
commit
08a8988462
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@ -32,22 +32,13 @@
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#include "target_internal.h"
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#include "cortexm.h"
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#if PC_HOSTED == 1
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#define DEBUG_CH DEBUG_INFO
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#define ERROR_CH DEBUG_WARN
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#else
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#define DEBUG_CH(...) {} //DEBUG_WARN //(...) {}
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#define ERROR_CH DEBUG_WARN //DEBUG_WARN
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#endif
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extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff
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static int ch32f1_flash_erase(struct target_flash *f,
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static int ch32f1_flash_erase(struct target_flash *f,
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target_addr addr, size_t len);
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static int ch32f1_flash_write(struct target_flash *f,
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static int ch32f1_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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// these are common with stm32f1/gd32f1/...
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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@ -76,9 +67,6 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff
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#define FLASH_SR_EOP (1<<5) // End of programming
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#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
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/**
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\fn ch32f1_add_flash
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\brief "fast" flash driver for CH32F10x chips
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@ -104,7 +92,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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#define WAIT_BUSY() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if(target_check_error(t)) { \
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ERROR_CH("ch32f1 flash write: comm error\n"); \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (sr & FLASH_SR_BSY);
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@ -112,7 +100,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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#define WAIT_EOP() do { \
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sr = target_mem_read32(t, FLASH_SR); \
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if(target_check_error(t)) { \
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ERROR_CH("ch32f1 flash write: comm error\n"); \
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DEBUG_WARN("ch32f1 flash write: comm error\n"); \
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return -1; \
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} \
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} while (!(sr & FLASH_SR_EOP));
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@ -120,18 +108,18 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP)
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#define SET_CR(bit) { ct = target_mem_read32(t, FLASH_CR); \
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ct|=(bit); \
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ct |= (bit); \
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target_mem_write32(t, FLASH_CR, ct);}
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#define CLEAR_CR(bit) {ct = target_mem_read32(t, FLASH_CR); \
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ct&=~(bit); \
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ct &= ~(bit); \
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target_mem_write32(t, FLASH_CR, ct);}
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// Which one is the right value ?
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#define MAGIC_WORD 0x100
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// #define MAGIC_WORD 0x1000
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#define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \
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#define MAGIC(adr) { magic = target_mem_read32(t,(adr) ^ MAGIC_WORD); \
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target_mem_write32(t, FLASH_MAGIC , magic); }
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/**
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@ -140,7 +128,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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*/
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static int ch32f1_flash_unlock(target *t)
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{
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DEBUG_CH("CH32: flash unlock \n");
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DEBUG_INFO("CH32: flash unlock \n");
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target_mem_write32(t, FLASH_KEYR , KEY1);
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target_mem_write32(t, FLASH_KEYR , KEY2);
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@ -148,16 +136,17 @@ static int ch32f1_flash_unlock(target *t)
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1);
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2);
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uint32_t cr = target_mem_read32(t, FLASH_CR);
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if (cr & FLASH_CR_FLOCK_CH32){
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ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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if (cr & FLASH_CR_FLOCK_CH32) {
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DEBUG_WARN("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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return -1;
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}
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return 0;
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}
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static int ch32f1_flash_lock(target *t)
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{
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volatile uint32_t ct;
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DEBUG_CH("CH32: flash lock \n");
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DEBUG_INFO("CH32: flash lock \n");
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SET_CR(FLASH_CR_LOCK);
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return 0;
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}
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@ -166,28 +155,24 @@ static int ch32f1_flash_lock(target *t)
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\brief identify the ch32f1 chip
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Actually grab all cortex m3 with designer = arm not caught earlier...
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*/
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bool ch32f1_probe(target *t)
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{
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t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
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if ((t->cpuid & CPUID_PARTNO_MASK) != CORTEX_M3)
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if ((t->cpuid & CPUID_PARTNO_MASK) != CORTEX_M3 || t->idcode != 0x410) // only ch32f103
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return false;
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if(t->idcode !=0x410) { // only ch32f103
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return false;
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}
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// try to flock
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ch32f1_flash_lock(t);
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// if this fails it is not a CH32 chip
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if(ch32f1_flash_unlock(t)) {
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if (ch32f1_flash_unlock(t))
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return false;
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}
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uint32_t signature = target_mem_read32(t, FLASHSIZE);
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uint32_t flashSize = signature & 0xFFFF;
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target_add_ram(t, 0x20000000, 0x5000);
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ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize*1024, 128);
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ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize * 1024, 128);
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target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD/VL-LD/VL-MD");
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t->driver = "CH32F1 medium density (stm32f1 clone)";
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return true;
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@ -196,26 +181,26 @@ bool ch32f1_probe(target *t)
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\fn ch32f1_flash_erase
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\brief fast erase of CH32
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*/
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int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
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int ch32f1_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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volatile uint32_t ct, sr, magic;
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target *t = f->t;
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DEBUG_CH("CH32: flash erase \n");
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DEBUG_INFO("CH32: flash erase \n");
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if (ch32f1_flash_unlock(t)) {
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ERROR_CH("CH32: Unlock failed\n");
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DEBUG_WARN("CH32: Unlock failed\n");
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return -1;
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}
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// Fast Erase 128 bytes pages (ch32 mode)
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while(len) {
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while (len) {
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SET_CR(FLASH_CR_FTER_CH32);// CH32 PAGE_ER
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/* write address to FMA */
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target_mem_write32(t, FLASH_AR , addr);
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target_mem_write32(t, FLASH_AR, addr);
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/* Flash page erase start instruction */
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SET_CR( FLASH_CR_STRT );
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SET_CR(FLASH_CR_STRT);
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WAIT_EOP();
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CLEAR_EOP();
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CLEAR_CR( FLASH_CR_STRT );
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CLEAR_CR(FLASH_CR_STRT);
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// Magic
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MAGIC(addr);
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if (len > 128)
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@ -226,8 +211,8 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
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}
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sr = target_mem_read32(t, FLASH_SR);
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ch32f1_flash_lock(t);
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if ((sr & SR_ERROR_MASK)) {
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ERROR_CH("ch32f1 flash erase error 0x%" PRIx32 "\n", sr);
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if (sr & SR_ERROR_MASK) {
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DEBUG_WARN("ch32f1 flash erase error 0x%" PRIx32 "\n", sr);
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return -1;
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}
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return 0;
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@ -241,13 +226,13 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
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NB: Just reading fff is not enough as it could be a transient previous operation value
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*/
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static bool ch32f1_wait_flash_ready(target *t, uint32_t adr)
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static bool ch32f1_wait_flash_ready(target *t, uint32_t addr)
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{
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uint32_t ff;
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for (int i = 0; i < 32; i++)
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ff = target_mem_read32(t, adr);
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uint32_t ff = 0;
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for (size_t i = 0; i < 32; i++)
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ff = target_mem_read32(t, addr);
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if (ff != 0xffffffffUL) {
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ERROR_CH("ch32f1 Not erased properly at %" PRIx32 " or flash access issue\n", adr);
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DEBUG_WARN("ch32f1 Not erased properly at %" PRIx32 " or flash access issue\n", addr);
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return false;
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}
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return true;
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@ -261,18 +246,18 @@ static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t of
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{
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volatile uint32_t ct, sr, magic;
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const uint32_t *ss = (const uint32_t *)(src+offset);
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uint32_t dd = dest+offset;
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uint32_t dd = dest + offset;
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SET_CR(FLASH_CR_FTPG_CH32);
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target_mem_write32(t, dd+0,ss[0]);
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target_mem_write32(t, dd+4,ss[1]);
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target_mem_write32(t, dd+8,ss[2]);
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target_mem_write32(t, dd+12,ss[3]);
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target_mem_write32(t, dd + 0, ss[0]);
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target_mem_write32(t, dd + 4, ss[1]);
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target_mem_write32(t, dd + 8, ss[2]);
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target_mem_write32(t, dd + 12, ss[3]);
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SET_CR(FLASH_CR_BUF_LOAD_CH32); /* BUF LOAD */
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WAIT_EOP();
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CLEAR_EOP();
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CLEAR_CR(FLASH_CR_FTPG_CH32);
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MAGIC((dest+offset));
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MAGIC(dest + offset);
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return 0;
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}
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/**
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@ -281,7 +266,7 @@ static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t of
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*/
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int ch32f1_buffer_clear(target *t)
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{
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volatile uint32_t ct,sr;
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volatile uint32_t ct, sr;
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SET_CR(FLASH_CR_FTPG_CH32); // Fast page program 4-
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SET_CR(FLASH_CR_BUF_RESET_CH32); // BUF_RESET 5-
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WAIT_BUSY(); // 6-
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@ -300,15 +285,15 @@ static int ch32f1_flash_write(struct target_flash *f,
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target *t = f->t;
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size_t length = len;
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#ifdef CH32_VERIFY
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target_addr orgDest=dest;
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const void *orgSrc=src;
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target_addr org_dest = dest;
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const void *org_src = src;
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#endif
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DEBUG_CH("CH32: flash write 0x%x ,size=%d\n",dest,len);
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DEBUG_INFO("CH32: flash write 0x%x ,size=%d\n", dest, len);
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while(length > 0)
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while (length > 0)
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{
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if(ch32f1_flash_unlock(t)) {
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ERROR_CH("ch32f1 cannot fast unlock\n");
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if (ch32f1_flash_unlock(t)) {
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DEBUG_WARN("ch32f1 cannot fast unlock\n");
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return -1;
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}
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WAIT_BUSY();
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@ -316,12 +301,12 @@ static int ch32f1_flash_write(struct target_flash *f,
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// Buffer reset...
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ch32f1_buffer_clear(t);
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// Load 128 bytes to buffer
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if(!ch32f1_wait_flash_ready(t,dest)) {
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if (!ch32f1_wait_flash_ready(t,dest))
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return -1;
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}
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for(int i = 0; i < 8; i++) {
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if(ch32f1_upload(t,dest,src, 16*i)) {
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ERROR_CH("Cannot upload to buffer\n");
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for (size_t i = 0; i < 8; i++) {
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if (ch32f1_upload(t, dest, src, i * 16U)) {
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DEBUG_WARN("Cannot upload to buffer\n");
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return -1;
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}
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}
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@ -333,10 +318,10 @@ static int ch32f1_flash_write(struct target_flash *f,
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CLEAR_EOP();
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CLEAR_CR(FLASH_CR_FTPG_CH32);
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MAGIC((dest));
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MAGIC(dest);
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// next
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if(length > 128)
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if (length > 128)
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length -=128;
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else
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length = 0;
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@ -345,24 +330,23 @@ static int ch32f1_flash_write(struct target_flash *f,
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sr = target_mem_read32(t, FLASH_SR); // 13
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ch32f1_flash_lock(t);
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if ((sr & SR_ERROR_MASK) ) {
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ERROR_CH("ch32f1 flash write error 0x%" PRIx32 "\n", sr);
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if (sr & SR_ERROR_MASK) {
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DEBUG_WARN("ch32f1 flash write error 0x%" PRIx32 "\n", sr);
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return -1;
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}
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}
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#ifdef CH32_VERIFY
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DEBUG_CH("Verifying\n");
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size_t i = 0;
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for(i = 0; i < len; i+= 4)
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DEBUG_INFO("Verifying\n");
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for (size_t i = 0; i < len; i += 4)
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{
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uint32_t mem=target_mem_read32(t, orgDest+i);
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uint32_t mem2=*(uint32_t *)(orgSrc+i);
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if(mem!=mem2)
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const uint32_t expected = *(uint32_t *)(org_src + i);
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const uint32_t actual = target_mem_read32(t, org_dest + i);
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if (expected != actual)
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{
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ERROR_CH(">>>>write mistmatch at address 0x%x\n",orgDest+i);
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ERROR_CH(">>>>expected 0x%x\n",mem2);
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ERROR_CH(">>>>flash 0x%x\n",mem);
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DEBUG_WARN(">>>>write mistmatch at address 0x%x\n", org_dest + i);
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DEBUG_WARN(">>>>expected: 0x%x\n", expected);
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DEBUG_WARN(">>>> actual: 0x%x\n", actual);
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return -1;
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}
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}
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@ -370,4 +354,3 @@ static int ch32f1_flash_write(struct target_flash *f,
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return 0;
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}
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// EOF
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