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target/adiv5: saner designer code handling and cleanup 

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
This commit is contained in:
Rafael Silva 2022-07-22 18:08:44 +01:00 committed by Rachel Mant
parent ce3d80528e
commit 0942d7047a
6 changed files with 265 additions and 226 deletions
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359
src/target/adiv5.c
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@ -80,7 +80,7 @@ enum cid_class {
/* 0xC */ /* Reserved */
cidc_dess = 0xD, /* OptimoDE Data Engine SubSystem (DESS) component */
cidc_gipc = 0xE, /* Generic IP Component */
cidc_pcp = 0xF, /* PrimeCell peripheral */
cidc_sys = 0xF, /* CoreLink, PrimeCell, or other system component with no standard register layout */
cidc_unknown = 0x10
};
@ -96,22 +96,29 @@ static const char *const cidc_debug_strings[] = {
[0xC] = "R", /* 0xC */
[cidc_dess] = "OptimoDE Data Engine SubSystem component", /* 0xD */
[cidc_gipc] = "Generic IP component", /* 0xE */
[cidc_pcp] = "PrimeCell peripheral", /* 0xF */
[cidc_sys] = "Non STD System component", /* 0xF */
[cidc_unknown] = "Unknown component class" /* 0x10 */
};
#endif
#define PIDR0_OFFSET 0xFE0 /* DBGPID0 */
#define PIDR1_OFFSET 0xFE4 /* DBGPID1 */
#define PIDR2_OFFSET 0xFE8 /* DBGPID2 */
#define PIDR3_OFFSET 0xFEC /* DBGPID3 */
#define PIDR4_OFFSET 0xFD0 /* DBGPID4 */
#define PIDR5_OFFSET 0xFD4 /* DBGPID5 (Reserved) */
#define PIDR6_OFFSET 0xFD8 /* DBGPID6 (Reserved) */
#define PIDR7_OFFSET 0xFDC /* DBGPID7 (Reserved) */
#define PIDR_REV_MASK 0x0FFF00000ULL /* Revision bits. */
#define PIDR_PN_MASK 0x000000FFFULL /* Part number bits. */
#define PIDR_ARM_BITS 0x4000BB000ULL /* These make up the ARM JEP-106 code. */
#define PIDR0_OFFSET 0xFE0 /* DBGPID0 */
#define PIDR1_OFFSET 0xFE4 /* DBGPID1 */
#define PIDR2_OFFSET 0xFE8 /* DBGPID2 */
#define PIDR3_OFFSET 0xFEC /* DBGPID3 */
#define PIDR4_OFFSET 0xFD0 /* DBGPID4 */
#define PIDR5_OFFSET 0xFD4 /* DBGPID5 (Reserved) */
#define PIDR6_OFFSET 0xFD8 /* DBGPID6 (Reserved) */
#define PIDR7_OFFSET 0xFDC /* DBGPID7 (Reserved) */
#define PIDR_JEP106_CONT_OFFSET 32ULL /*JEP-106 Continuation Code offset */
#define PIDR_JEP106_CONT_MASK (0xFULL << PIDR_JEP106_CONT_OFFSET) /*JEP-106 Continuation Code mask */
#define PIDR_REV_OFFSET 20ULL /* Revision bits offset */
#define PIDR_REV_MASK (0xFFFULL << PIDR_REV_OFFSET) /* Revision bits mask */
#define PIDR_JEP106_USED_OFFSET 19ULL /* JEP-106 code used flag offset */
#define PIDR_JEP106_USED (1ULL << PIDR_JEP106_USED_OFFSET) /* JEP-106 code used flag */
#define PIDR_JEP106_CODE_OFFSET 12ULL /* JEP-106 code offset */
#define PIDR_JEP106_CODE_MASK (0x7FULL << PIDR_JEP106_CODE_OFFSET) /* JEP-106 code mask */
#define PIDR_PN_MASK (0xFFFULL) /* Part number */
#define DEVTYPE_OFFSET 0xFCCU /* CoreSight Device Type Register */
#define DEVARCH_OFFSET 0xFBCU /* CoreSight Device Architecture Register */
@ -128,9 +135,9 @@ enum arm_arch {
};
#ifdef ENABLE_DEBUG
#define PIDR_PN_BIT_STRINGS(...) __VA_ARGS__
#define ARM_COMPONENT_STR(...) __VA_ARGS__
#else
#define PIDR_PN_BIT_STRINGS(...)
#define ARM_COMPONENT_STR(...)
#endif
/* The part number list was adopted from OpenOCD:
@ -140,32 +147,27 @@ enum arm_arch {
* refer to ARM Debug Interface v5 Architecture Specification. Based on the
* document the pidr is 64 bit long and has the following interpratiation:
* |7 ID7 reg 0|7 ID6 reg 0|7 ID5 reg 0|7 ID4 reg 0|
* |0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0| | | | |1|0|0|0|
* |0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0| | | | | | | | |
* |63 56|55 48|47 40|39 36|35 32|
* \_______________________ ______________________/\___ __/\___ ___/
* V V V
* Reserved, RAZ 4KB |
* count |
* JEP-106
* Continuation Code
* Continuation Code (only valid for JEP-106 codes)
*
* |7 ID3 reg 0|7 ID2 reg 0|7 ID1 reg 0|7 ID0 reg 0|
* | | | | | | | | | | | | |1|0|1|1|1|0|1|1| | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
* |31 28|27 24|23 20|||18 | 12|11 | 0|
* \___ __/\__ ___/\___ __/ |\______ _____/\___________ ___________/
* V V V | V V
* RevAnd | Revision | JEP-106 Part number
* | | ID code
* RevAnd | Revision | JEP-106 ID Part number
* | | (no parity)
* Customer 19
* modified `- JEP-106 code is used
*
* JEP-106 is a JEDEC standard assigning manufacturer IDs to different
* manufacturers in case of ARM the full code consisting of the JEP-106
* Continuation code followed by the code used bit and the JEP-106 code itself
* results in the code 0x4BB. These are the bits filled in the above bit table.
*
* We left out some of the Part numbers included in OpenOCD, we only include
* the ones that have ARM as the designer.
* only a subset of Part numbers are listed,
* the ones that have ARM as the designer code.
*
* To properly identify ADIv6 CoreSight components, two additional fields,
* DEVTYPE and ARCHID are read.
@ -186,90 +188,87 @@ static const struct {
const char *type;
const char *full;
#endif
} pidr_pn_bits[] = {
{0x000, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M3 SCS", "(System Control Space)")},
{0x001, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("Cortex-M3 ITM", "(Instrumentation Trace Module)")},
{0x002, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 DWT", "(Data Watchpoint and Trace)")},
{0x003, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 FBP", "(Flash Patch and Breakpoint)")},
{0x008, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M0 SCS", "(System Control Space)")},
{0x00a, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 DWT", "(Data Watchpoint and Trace)")},
{0x00b, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 BPU", "(Breakpoint Unit)")},
{0x00c, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M4 SCS", "(System Control Space)")},
{0x00d, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
{0x00e, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 FBP", "(Flash Patch and Breakpoint)")},
{0x101, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("System TSGEN", "(Time Stamp Generator)")},
{0x471, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 ROM", "(Cortex-M0 ROM)")},
{0x490, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
{0x4c0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0+ ROM", "(Cortex-M0+ ROM)")},
{0x4c3, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ROM", "(Cortex-M3 ROM)")},
{0x4c4, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ROM", "(Cortex-M4 ROM)")},
} arm_component_lut[] = {
{0x000, 0x00, 0, aa_cortexm, cidc_gipc, ARM_COMPONENT_STR("Cortex-M3 SCS", "(System Control Space)")},
{0x001, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 ITM", "(Instrumentation Trace Module)")},
{0x002, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 DWT", "(Data Watchpoint and Trace)")},
{0x003, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 FBP", "(Flash Patch and Breakpoint)")},
{0x008, 0x00, 0, aa_cortexm, cidc_gipc, ARM_COMPONENT_STR("Cortex-M0 SCS", "(System Control Space)")},
{0x00a, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M0 DWT", "(Data Watchpoint and Trace)")},
{0x00b, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M0 BPU", "(Breakpoint Unit)")},
{0x00c, 0x00, 0, aa_cortexm, cidc_gipc, ARM_COMPONENT_STR("Cortex-M4 SCS", "(System Control Space)")},
{0x00d, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight ETM11", "(Embedded Trace)")},
{0x00e, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 FBP", "(Flash Patch and Breakpoint)")},
{0x101, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("System TSGEN", "(Time Stamp Generator)")},
{0x471, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M0 ROM", "(Cortex-M0 ROM)")},
{0x490, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
{0x4c0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M0+ ROM", "(Cortex-M0+ ROM)")},
{0x4c3, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 ROM", "(Cortex-M3 ROM)")},
{0x4c4, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M4 ROM", "(Cortex-M4 ROM)")},
{0x4c7, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("Cortex-M7 PPB", "(Cortex-M7 Private Peripheral Bus ROM Table)")},
{0x4c8, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ROM", "(Cortex-M7 ROM)")},
{0x906, 0x14, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI", "(Cross Trigger)")},
{0x907, 0x21, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB", "(Trace Buffer)")},
{0x908, 0x12, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CSTF", "(Trace Funnel)")},
{0x910, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM9", "(Embedded Trace)")},
{0x912, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU", "(Trace Port Interface Unit)")},
ARM_COMPONENT_STR("Cortex-M7 PPB", "(Cortex-M7 Private Peripheral Bus ROM Table)")},
{0x4c8, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 ROM", "(Cortex-M7 ROM)")},
{0x906, 0x14, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight CTI", "(Cross Trigger)")},
{0x907, 0x21, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight ETB", "(Trace Buffer)")},
{0x908, 0x12, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight CSTF", "(Trace Funnel)")},
{0x910, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight ETM9", "(Embedded Trace)")},
{0x912, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight TPIU", "(Trace Port Interface Unit)")},
{0x913, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
{0x914, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight SWO", "(Single Wire Output)")},
{0x917, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight HTM", "(AHB Trace Macrocell)")},
{0x920, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
{0x921, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 ETM", "(Embedded Trace)")},
{0x922, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 CTI", "(Cross Trigger)")},
{0x923, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 TPIU", "(Trace Port Interface Unit)")},
{0x924, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ETM", "(Embedded Trace)")},
{0x925, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ETM", "(Embedded Trace)")},
{0x930, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 ETM", "(Embedded Trace)")},
ARM_COMPONENT_STR("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
{0x914, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight SWO", "(Single Wire Output)")},
{0x917, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight HTM", "(AHB Trace Macrocell)")},
{0x920, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight ETM11", "(Embedded Trace)")},
{0x921, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A8 ETM", "(Embedded Trace)")},
{0x922, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A8 CTI", "(Cross Trigger)")},
{0x923, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 TPIU", "(Trace Port Interface Unit)")},
{0x924, 0x13, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M3 ETM", "(Embedded Trace)")},
{0x925, 0x13, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M4 ETM", "(Embedded Trace)")},
{0x930, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-R4 ETM", "(Embedded Trace)")},
{0x932, 0x31, 0x0a31, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("CoreSight MTB-M0+", "(Simple Execution Trace)")},
ARM_COMPONENT_STR("CoreSight MTB-M0+", "(Simple Execution Trace)")},
{0x941, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
ARM_COMPONENT_STR("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
{0x950, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")},
ARM_COMPONENT_STR("CoreSight Component", "(unidentified Cortex-A9 component)")},
{0x955, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")},
{0x956, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 ETM", "(Embedded Trace)")},
{0x95f, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PTM", "(Program Trace Macrocell)")},
{0x961, 0x32, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TMC", "(Trace Memory Controller)")},
{0x962, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
{0x963, 0x63, 0x0a63, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
{0x975, 0x13, 0x4a13, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ETM", "(Embedded Trace)")},
{0x9a0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight PMU", "(Performance Monitoring Unit)")},
{0x9a1, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
{0x9a6, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M0+ CTI", "(Cross Trigger Interface)")},
{0x9a9, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 TPIU", "(Trace Port Interface Unit)")},
{0x9a5, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A5 ETM", "(Embedded Trace)")},
{0x9a7, 0x16, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 PMU", "(Performance Monitor Unit)")},
{0x9af, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PMU", "(Performance Monitor Unit)")},
{0xc05, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A5 Debug", "(Debug Unit)")},
{0xc07, 0x15, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A7 Debug", "(Debug Unit)")},
{0xc08, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A8 Debug", "(Debug Unit)")},
{0xc09, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A9 Debug", "(Debug Unit)")},
{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown,
PIDR_PN_BIT_STRINGS("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
{0xc14, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Atmel DSU", "(Device Service Unit)")},
{0xd20, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(System Control Space)")},
{0xd20, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Trace Port Interface Unit)")},
{0xd20, 0x13, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Embedded Trace)")},
{0xd20, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Micro Trace Buffer)")},
{0xd20, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Data Watchpoint and Trace)")},
{0xd20, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Breakpoint Unit)")},
{0xd20, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Cross Trigger)")},
{0xd21, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(System Control Space)")},
{0xd21, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Micro Trace Buffer)")},
{0xd21, 0x43, 0x1a01, aa_nosupport, cidc_dc,
PIDR_PN_BIT_STRINGS("Cortex-M33", "(Instrumentation Trace Macrocell)")},
{0xd21, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Data Watchpoint and Trace)")},
{0xd21, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Breakpoint Unit)")},
{0xd21, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Cross Trigger)")},
{0xd21, 0x13, 0x4a13, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Embedded Trace)")},
{0xd21, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Trace Port Interface Unit)")},
{0xfff, 0x00, 0, aa_end, cidc_unknown, PIDR_PN_BIT_STRINGS("end", "end")}};
ARM_COMPONENT_STR("CoreSight Component", "(unidentified Cortex-A5 component)")},
{0x956, 0x13, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A7 ETM", "(Embedded Trace)")},
{0x95f, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 PTM", "(Program Trace Macrocell)")},
{0x961, 0x32, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight TMC", "(Trace Memory Controller)")},
{0x962, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight STM", "(System Trace Macrocell)")},
{0x963, 0x63, 0x0a63, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight STM", "(System Trace Macrocell)")},
{0x975, 0x13, 0x4a13, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 ETM", "(Embedded Trace)")},
{0x9a0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight PMU", "(Performance Monitoring Unit)")},
{0x9a1, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
{0x9a6, 0x14, 0x1a14, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M0+ CTI", "(Cross Trigger Interface)")},
{0x9a9, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 TPIU", "(Trace Port Interface Unit)")},
{0x9a5, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A5 ETM", "(Embedded Trace)")},
{0x9a7, 0x16, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A7 PMU", "(Performance Monitor Unit)")},
{0x9af, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 PMU", "(Performance Monitor Unit)")},
{0xc05, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A5 Debug", "(Debug Unit)")},
{0xc07, 0x15, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A7 Debug", "(Debug Unit)")},
{0xc08, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A8 Debug", "(Debug Unit)")},
{0xc09, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A9 Debug", "(Debug Unit)")},
{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
{0xc14, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Atmel DSU", "(Device Service Unit)")},
{0xd20, 0x00, 0x2a04, aa_cortexm, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(System Control Space)")},
{0xd20, 0x11, 0, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Trace Port Interface Unit)")},
{0xd20, 0x13, 0, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Embedded Trace)")},
{0xd20, 0x31, 0x0a31, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Micro Trace Buffer)")},
{0xd20, 0x00, 0x1a02, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Data Watchpoint and Trace)")},
{0xd20, 0x00, 0x1a03, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Breakpoint Unit)")},
{0xd20, 0x14, 0x1a14, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Cross Trigger)")},
{0xd21, 0x00, 0x2a04, aa_cortexm, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(System Control Space)")},
{0xd21, 0x31, 0x0a31, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Micro Trace Buffer)")},
{0xd21, 0x43, 0x1a01, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Instrumentation Trace Macrocell)")},
{0xd21, 0x00, 0x1a02, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Data Watchpoint and Trace)")},
{0xd21, 0x00, 0x1a03, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Breakpoint Unit)")},
{0xd21, 0x14, 0x1a14, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Cross Trigger)")},
{0xd21, 0x13, 0x4a13, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Embedded Trace)")},
{0xd21, 0x11, 0, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M33", "(Trace Port Interface Unit)")},
{0xfff, 0x00, 0, aa_end, cidc_unknown, ARM_COMPONENT_STR("end", "end")},
};
extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
@ -436,24 +435,26 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
}
/* Return true if we find a debuggable device.*/
static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t recursion, const size_t num_entry)
{
(void)num_entry;
addr &= 0xfffff000; /* Mask out base address */
if (addr == 0) /* No rom table on this AP */
return;
volatile uint32_t cidr;
cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
const volatile uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
if (ap->dp->fault) {
DEBUG_WARN("CIDR read timeout on AP%d, aborting.\n", ap->apsel);
return;
}
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE)
return;
#if defined(ENABLE_DEBUG)
char indent[recursion + 1];
for (int i = 0; i < recursion; i++)
for (size_t i = 0; i < recursion; i++)
indent[i] = ' ';
indent[recursion] = 0;
#endif
@ -470,29 +471,40 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
return;
}
uint64_t pidr = adiv5_ap_read_pidr(ap, addr);
/* Extract Component ID class nibble */
uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
const uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
const uint64_t pidr = adiv5_ap_read_pidr(ap, addr);
uint16_t designer_code;
if (pidr & PIDR_JEP106_USED) {
/* (OFFSET - 8) because we want it on bits 11:8 of new code, see "JEP-106 code list" */
designer_code = (pidr & PIDR_JEP106_CONT_MASK) >> (PIDR_JEP106_CONT_OFFSET - 8) |
(pidr & PIDR_JEP106_CODE_MASK) >> PIDR_JEP106_CODE_OFFSET;
if (designer_code == JEP106_MANUFACTURER_ERRATA_STM32WX || designer_code == JEP106_MANUFACTURER_ERRATA_CS) {
/**
* see 'JEP-106 code list' for context, here we are aliasing codes that are non compliant with the
* JEP-106 standard to their expected codes, this is later used to determine the correct probe function.
*/
DEBUG_WARN("Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
designer_code = JEP106_MANUFACTURER_STM;
}
} else {
/* legacy ascii code */
designer_code = (pidr & PIDR_JEP106_CODE_MASK) >> PIDR_JEP106_CODE_OFFSET | ASCII_CODE_FLAG;
}
/* Extract part number from the part id register. */
const uint16_t part_number = pidr & PIDR_PN_MASK;
/* ROM table */
if (cid_class == cidc_romtab) {
uint16_t designer = ((pidr >> 24) & 0xf00) | ((pidr >> 12) & 0x7f);
uint16_t partno = pidr & 0xfff;
#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
/* Check SYSMEM bit */
uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) & ADIV5_ROM_MEMTYPE_SYSMEM;
if (adiv5_dp_error(ap->dp)) {
DEBUG_WARN("Fault reading ROM table entry\n");
}
DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%08" PRIx32 ", designer %3x Partno %3x\n", addr, memtype,
designer, partno);
#endif
if (recursion == 0) {
ap->ap_designer = designer;
ap->ap_partno = partno;
if ((ap->ap_designer == AP_DESIGNER_ATMEL) && (ap->ap_partno == 0xcd0)) {
ap->designer_code = designer_code;
ap->ap_partno = part_number;
if ((ap->designer_code == JEP106_MANUFACTURER_ATMEL) && (ap->ap_partno == 0xcd0)) {
#define SAMX5X_DSU_CTRLSTAT 0x41002100
#define SAMX5X_STATUSB_PROT (1 << 16)
uint32_t ctrlstat = adiv5_mem_read32(ap, SAMX5X_DSU_CTRLSTAT);
@ -506,8 +518,21 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
}
}
}
for (int i = 0; i < 960; i++) {
#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
/* Check SYSMEM bit */
uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) & ADIV5_ROM_MEMTYPE_SYSMEM;
if (adiv5_dp_error(ap->dp)) {
DEBUG_WARN("Fault reading ROM table entry\n");
}
DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%08" PRIx32 ", Manufacturer %3x Partno %3x\n", addr, memtype,
designer_code, part_number);
#endif
for (size_t i = 0; i < 960; i++) {
adiv5_dp_error(ap->dp);
uint32_t entry = adiv5_mem_read32(ap, addr + i * 4);
if (adiv5_dp_error(ap->dp)) {
DEBUG_WARN("%sFault reading ROM table entry %d\n", indent, i);
@ -526,12 +551,11 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
adiv5_component_probe(ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET), recursion + 1, i);
}
DEBUG_INFO("%sROM: Table END\n", indent);
} else {
/* Check if the component was designed by ARM, we currently do not support,
* any components by other designers.
*/
if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
DEBUG_WARN("%s0x%" PRIx32 ": 0x%02" PRIx32 "%08" PRIx32 " <- does not match ARM JEP-106\n", indent, addr,
if (designer_code != JEP106_MANUFACTURER_ARM) {
/* non arm components not supported currently */
DEBUG_WARN("%s0x%" PRIx32 ": 0x%02" PRIx32 "%08" PRIx32 " Non ARM component ignored\n", indent, addr,
(uint32_t)(pidr >> 32), (uint32_t)pidr);
return;
}
@ -549,46 +573,43 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
}
}
/* Extract part number from the part id register. */
uint16_t part_number = pidr & PIDR_PN_MASK;
/* Find the part number in our part list and run the appropriate probe
* routine if applicable.
*/
int i;
for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
if ((pidr_pn_bits[i].part_number == part_number) && (pidr_pn_bits[i].dev_type == dev_type) &&
(pidr_pn_bits[i].arch_id == arch_id)) {
DEBUG_INFO("%s%d 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
" ARCHID = 0x%04" PRIx16 ")",
indent + 1, num_entry, addr, cidc_debug_strings[cid_class], pidr_pn_bits[i].type,
pidr_pn_bits[i].full, (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
/* Perform sanity check, if we know what to expect as
* component ID class.
*/
if ((pidr_pn_bits[i].cidc != cidc_unknown) && (cid_class != pidr_pn_bits[i].cidc)) {
DEBUG_WARN("%sWARNING: \"%s\" !match expected \"%s\"\n", indent + 1, cidc_debug_strings[cid_class],
cidc_debug_strings[pidr_pn_bits[i].cidc]);
}
switch (pidr_pn_bits[i].arch) {
case aa_cortexm:
DEBUG_INFO("%s-> cortexm_probe\n", indent + 1);
cortexm_probe(ap);
break;
case aa_cortexa:
DEBUG_INFO("\n -> cortexa_probe\n");
cortexa_probe(ap, addr);
break;
default:
DEBUG_INFO("\n");
break;
}
/* Find the part number in our part list and run the appropriate probe routine if applicable. */
size_t i;
for (i = 0; arm_component_lut[i].arch != aa_end; i++) {
if (arm_component_lut[i].part_number != part_number || arm_component_lut[i].dev_type != dev_type ||
arm_component_lut[i].arch_id != arch_id)
continue;
DEBUG_INFO("%s%d 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
" ARCHID = 0x%04" PRIx16 ")\n",
indent + 1, num_entry, addr, cidc_debug_strings[cid_class], arm_component_lut[i].type,
arm_component_lut[i].full, (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
/* Perform sanity check, if we know what to expect as * component ID class. */
if (arm_component_lut[i].cidc != cidc_unknown && cid_class != arm_component_lut[i].cidc) {
DEBUG_WARN("%sWARNING: \"%s\" !match expected \"%s\"\n", indent + 1, cidc_debug_strings[cid_class],
cidc_debug_strings[arm_component_lut[i].cidc]);
}
switch (arm_component_lut[i].arch) {
case aa_cortexm:
DEBUG_INFO("%s-> cortexm_probe\n", indent + 1);
cortexm_probe(ap);
break;
case aa_cortexa:
DEBUG_INFO("%s-> cortexa_probe\n", indent + 1);
cortexa_probe(ap, addr);
break;
default:
break;
}
break;
}
if (pidr_pn_bits[i].arch == aa_end) {
DEBUG_WARN("%s0x%" PRIx32 ": %s - Unknown (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
if (arm_component_lut[i].arch == aa_end) {
DEBUG_WARN("%s%d 0x%" PRIx32 ": %s - Unknown (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
" ARCHID = 0x%04" PRIx16 ")\n",
indent, addr, cidc_debug_strings[cid_class], (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
indent, num_entry, addr, cidc_debug_strings[cid_class], (uint32_t)(pidr >> 32), (uint32_t)pidr,
dev_type, arch_id);
}
}
return;

80
src/target/adiv5.h
View File

@ -88,32 +88,6 @@
#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8U)
#define ADIV5_AP_IDR ADIV5_AP_REG(0xFCU)
/* Known designers seen in SYSROM-PIDR. Ignore Bit 0 from
* the designer bits to get JEDEC Ids with bit 7 ignored.*/
#define AP_DESIGNER_FREESCALE 0x00e
#define AP_DESIGNER_TEXAS 0x017
#define AP_DESIGNER_ATMEL 0x01f
#define AP_DESIGNER_STM 0x020
/* CPU2 for STM32W(L|B) uses ARM JEDEC continuation (4) and
* not STM ARM JEDEC continuation (0) as for CPU1.
* See RM0453
* https://www.st.com/resource/en/reference_manual/rm0453-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf :
* 38.8.2 CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4)
* vs
* 38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4)
*/
#define AP_DESIGNER_STM32WX 0x420
#define AP_DESIGNER_CYPRESS 0x034
#define AP_DESIGNER_INFINEON 0x041
#define AP_DESIGNER_NORDIC 0x244
#define AP_DESIGNER_ARM 0x43b
/*LPC845 with designer 501. Strange!? */
#define AP_DESIGNER_SPECULAR 0x501
#define AP_DESIGNER_CS 0x555
#define AP_DESIGNER_ENERGY_MICRO 0x673
#define AP_DESIGNER_GIGADEVICE 0x751
#define AP_DESIGNER_RASPBERRY 0x927
/* AP Control and Status Word (CSW) */
#define ADIV5_AP_CSW_DBGSWENABLE (1U << 31U)
/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
@ -152,6 +126,58 @@
#define SWDP_ACK_WAIT 0x02U
#define SWDP_ACK_FAULT 0x04U
/* JEP-106 code list
* JEP-106 is a JEDEC standard assigning IDs to different manufacturers
* the codes in this list are encoded as 16 bit values,
* with the first bit marking a legacy code (ASCII, not JEP106), the following 3 bits being NULL/unused
* the following 4 bits the number of continuation codes (see JEP106 continuation scheme),
* and the last 8 bits being the code itself (without parity, bit 7 is always 0).
*
* |15 |11 |7|6 0|
* | | | | | | | | |0| | | | | | | |
* |\____/ \______/|\_____________/
* | V V | V
* | Unused Cont | code
* | Code |
* \_ Legacy flag \_ Parity bit (always 0)
*/
#define ASCII_CODE_FLAG (1U << 15U) /* flag the code as legacy ASCII */
#define JEP106_MANUFACTURER_ARM 0x43BU /* ARM Ltd. */
#define JEP106_MANUFACTURER_FREESCALE 0x00eU /* Freescale */
#define JEP106_MANUFACTURER_TEXAS 0x017U /* Texas Instruments */
#define JEP106_MANUFACTURER_ATMEL 0x01fU /* Atmel */
#define JEP106_MANUFACTURER_STM 0x020U /* STMicroelectronics */
#define JEP106_MANUFACTURER_CYPRESS 0x034U /* Cypress Semiconductor */
#define JEP106_MANUFACTURER_INFINEON 0x041U /* Infineon Technologies */
#define JEP106_MANUFACTURER_NORDIC 0x244U /* Nordic Semiconductor */
#define JEP106_MANUFACTURER_SPECULAR 0x501U /* LPC845 with code 501. Strange!? Specular Networks */
#define JEP106_MANUFACTURER_ENERGY_MICRO 0x673U /* Energy Micro */
#define JEP106_MANUFACTURER_GIGADEVICE 0x751U /* GigaDevice */
#define JEP106_MANUFACTURER_RASPBERRY 0x927U /* Raspberry Pi */
/*
* This code is not listed in the JEP106 standard, but is used by some stm32f1 clones
* since we're not using this code elsewhere let's switch to the stm code.
*/
#define JEP106_MANUFACTURER_ERRATA_CS 0x555U
/* CPU2 for STM32W(L|B) uses ARM's JEP-106 continuation code (4) instead of
* STM's JEP-106 continuation code (0) like expected, CPU1 behaves as expected.
*
* See RM0453
* https://www.st.com/resource/en/reference_manual/rm0453-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf :
* 38.8.2 CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4)
* vs
* 38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4)
*
* let's call this an errata and switch to the "correct" continuation scheme.
*
* note: the JEP code 0x420 would belong to "Legend Silicon Corp." so in
* the unlikely event we need to support chips by them, here be dragons.
*/
#define JEP106_MANUFACTURER_ERRATA_STM32WX 0x420U
enum align {
ALIGN_BYTE = 0,
ALIGN_HALFWORD = 1,
@ -209,7 +235,7 @@ struct ADIv5_AP_s {
uint32_t csw;
uint32_t ap_cortexm_demcr; /* Copy of demcr when starting */
uint32_t ap_storage; /* E.g to hold STM32F7 initial DBGMCU_CR value.*/
uint16_t ap_designer;
uint16_t designer_code;
uint16_t ap_partno;
};

44
src/target/cortexm.c
View File

@ -279,8 +279,8 @@ bool cortexm_probe(ADIv5_AP_t *ap)
}
adiv5_ap_ref(ap);
t->t_designer = ap->ap_designer;
t->idcode = ap->ap_partno;
t->designer_code = ap->designer_code;
t->idcode = ap->ap_partno;
struct cortexm_priv *priv = calloc(1, sizeof(*priv));
if (!priv) { /* calloc failed: heap exhaustion */
DEBUG_WARN("calloc: failed in %s\n", __func__);
@ -332,7 +332,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
t->core = "M0";
break;
default:
if (ap->ap_designer != AP_DESIGNER_ATMEL) /* Protected Atmel device?*/{
if (ap->designer_code != JEP106_MANUFACTURER_ATMEL) /* Protected Atmel device?*/{
DEBUG_WARN("Unexpected CortexM CPUID partno %04" PRIx32 "\n", cpuid_partno);
}
}
@ -404,24 +404,18 @@ bool cortexm_probe(ADIv5_AP_t *ap)
} while (0)
#endif
switch (ap->ap_designer) {
case AP_DESIGNER_FREESCALE:
switch (ap->designer_code) {
case JEP106_MANUFACTURER_FREESCALE:
PROBE(kinetis_probe);
if (ap->ap_partno == 0x88c) {
t->driver = "MIMXRT10xx(no flash)";
target_halt_resume(t, 0);
}
break;
case AP_DESIGNER_CS:
PROBE(stm32f1_probe);
break;
case AP_DESIGNER_GIGADEVICE:
case JEP106_MANUFACTURER_GIGADEVICE:
PROBE(gd32f1_probe);
break;
case AP_DESIGNER_STM32WX:
PROBE(stm32l4_probe);
break;
case AP_DESIGNER_STM:
case JEP106_MANUFACTURER_STM:
PROBE(stm32f1_probe);
PROBE(stm32f4_probe);
PROBE(stm32h7_probe);
@ -429,43 +423,41 @@ bool cortexm_probe(ADIv5_AP_t *ap)
PROBE(stm32l4_probe);
PROBE(stm32g0_probe);
break;
case AP_DESIGNER_CYPRESS:
case JEP106_MANUFACTURER_CYPRESS:
DEBUG_WARN("Unhandled Cypress device\n");
break;
case AP_DESIGNER_INFINEON:
case JEP106_MANUFACTURER_INFINEON:
DEBUG_WARN("Unhandled Infineon device\n");
break;
case AP_DESIGNER_NORDIC:
case JEP106_MANUFACTURER_NORDIC:
PROBE(nrf51_probe);
break;
case AP_DESIGNER_ATMEL:
case JEP106_MANUFACTURER_ATMEL:
PROBE(samx7x_probe);
PROBE(sam4l_probe);
PROBE(samd_probe);
PROBE(samx5x_probe);
break;
case AP_DESIGNER_ENERGY_MICRO:
case JEP106_MANUFACTURER_ENERGY_MICRO:
PROBE(efm32_probe);
break;
case AP_DESIGNER_TEXAS:
case JEP106_MANUFACTURER_TEXAS:
PROBE(msp432_probe);
break;
case AP_DESIGNER_SPECULAR:
case JEP106_MANUFACTURER_SPECULAR:
PROBE(lpc11xx_probe); /* LPC845 */
break;
default:
if (ap->ap_designer != AP_DESIGNER_ARM) {
if (ap->designer_code != JEP106_MANUFACTURER_ARM) {
/* Report unexpected designers */
#if PC_HOSTED == 0
gdb_outf("Please report Designer %3x and Partno %3x and the "
"probed device\n", ap->ap_designer, ap->ap_partno);
gdb_outf("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code, ap->ap_partno);
#else
DEBUG_WARN("Please report Designer %3x and Partno %3x and the "
"probed device\n", ap->ap_designer, ap->ap_partno);
DEBUG_WARN("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code, ap->ap_partno);
#endif
}
if (ap->ap_partno == 0x4c0) { /* Cortex-M0+ ROM */
if ((ap->dp->targetid & 0xfff) == AP_DESIGNER_RASPBERRY)
if ((ap->dp->targetid & 0xfff) == JEP106_MANUFACTURER_RASPBERRY)
PROBE(rp_probe);
PROBE(lpc11xx_probe); /* LPC8 */
} else if (ap->ap_partno == 0x4c3) { /* Cortex-M3 ROM */

4
src/target/lpc11xx.c
View File

@ -172,7 +172,7 @@ lpc11xx_probe(target *t)
target_add_commands(t, lpc11xx_cmd_list, "LPC8N04");
return true;
}
if ((t->t_designer != AP_DESIGNER_SPECULAR) && idcode) {
if ((t->designer_code != JEP106_MANUFACTURER_SPECULAR) && idcode) {
DEBUG_INFO("LPC11xx: Unknown IDCODE 0x%08" PRIx32 "\n", idcode);
}
/* For LPC802, see UM11045 Rev. 1.4 Chapter 6.6.29 Table 84
@ -181,7 +181,7 @@ lpc11xx_probe(target *t)
* For LPC82x, see UM10800 Rev. 1.2 Chapter 5.6.34 Table 55
* For LPC83x, see UM11021 Rev. 1.1 Chapter 5.6.34 Table 53
* For LPC84x, see UM11029 Rev. 1.4 Chapter 8.6.49 Table 174
*
*
* Not documented, but the DEVICE_ID register at address 0x400483F8
* for the LPC8xx series is also valid for the LPC11xx "XL" and the
* LPC11U3x variants.

2
src/target/target.c
View File

@ -586,7 +586,7 @@ const char *target_core_name(target *t)
unsigned int target_designer(target *t)
{
return t->t_designer;
return t->designer_code;
}
unsigned int target_idcode(target *t)

2
src/target/target_internal.h
View File

@ -116,7 +116,7 @@ struct target_s {
/* target-defined options */
unsigned target_options;
uint16_t t_designer;
uint16_t designer_code;
uint16_t idcode;
void *target_storage;
union {