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Make Cortex M driver write DCCIMVAC (Data cache clean and invalidate by address to the PoC=Point of Coherency) prior to reading or writing each 32 bytes of RAM

This commit is contained in:
Nick Downing 2017-07-14 20:45:54 +10:00 committed by Gareth McMullin
parent 9a5b31c37b
commit 0e5b3ab00e
2 changed files with 35 additions and 0 deletions
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32
src/target/cortexm.c
View File

@ -181,11 +181,43 @@ ADIv5_AP_t *cortexm_ap(target *t)
static void cortexm_mem_read(target *t, void *dest, target_addr src, size_t len) static void cortexm_mem_read(target *t, void *dest, target_addr src, size_t len)
{ {
/* flush data cache for RAM regions that intersect requested region */
target_addr src_end = src + len; /* following code is NOP if wraparound */
/* requested region is [src, src_end) */
for (struct target_ram *r = t->ram; r; r = r->next) {
target_addr ram = r->start;
target_addr ram_end = r->start + r->length;
/* RAM region is [ram, ram_end) */
if (src > ram)
ram = src;
if (src_end < ram_end)
ram_end = src_end;
/* intersection is [ram, ram_end) */
for (ram &= ~0x1f; ram < ram_end; ram += 0x20)
adiv5_mem_write(cortexm_ap(t), CORTEXM_DCCIMVAC, &ram, 4);
}
adiv5_mem_read(cortexm_ap(t), dest, src, len); adiv5_mem_read(cortexm_ap(t), dest, src, len);
} }
static void cortexm_mem_write(target *t, target_addr dest, const void *src, size_t len) static void cortexm_mem_write(target *t, target_addr dest, const void *src, size_t len)
{ {
/* flush data cache for RAM regions that intersect requested region */
target_addr dest_end = dest + len; /* following code is NOP if wraparound */
/* requested region is [dest, dest_end) */
for (struct target_ram *r = t->ram; r; r = r->next) {
target_addr ram = r->start;
target_addr ram_end = r->start + r->length;
/* RAM region is [ram, ram_end) */
if (dest > ram)
ram = dest;
if (dest_end < ram_end)
ram_end = dest_end;
/* intersection is [ram, ram_end) */
for (ram &= ~0x1f; ram < ram_end; ram += 0x20)
adiv5_mem_write(cortexm_ap(t), CORTEXM_DCCIMVAC, &ram, 4);
}
adiv5_mem_write(cortexm_ap(t), dest, src, len); adiv5_mem_write(cortexm_ap(t), dest, src, len);
} }

3
src/target/cortexm.h
View File

@ -37,6 +37,9 @@
#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8) #define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC) #define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
/* Data cache clean and invalidate by address to the PoC=Point of Coherency */
#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xF70)
#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000) #define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */ /* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */