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cortexm: Refactored out the logic for reading the CPU ID into its own function

This commit is contained in:
dragonmux 2022-08-29 22:07:14 +01:00 committed by Piotr Esden-Tempski
parent 8d5caeaaff
commit 0edd8f0e67
2 changed files with 51 additions and 48 deletions
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82
src/target/cortexm.c
View File

@ -490,6 +490,48 @@ static void cortexm_priv_free(void *priv)
free(priv); free(priv);
} }
static void cortexm_read_cpuid(target *const t, const ADIv5_AP_t *const ap)
{
/* The CPUID register is defined in the ARMv7-M and ARMv8-M
* architecture manuals. The PARTNO field is implementation defined,
* that is, the actual values are found in the Technical Reference Manual
* for each Cortex-M core.
*/
t->cpuid = target_mem_read32(t, CORTEXM_CPUID);
const uint16_t cpuid_partno = t->cpuid & CPUID_PARTNO_MASK;
switch (cpuid_partno) {
case CORTEX_M33:
t->core = "M33";
break;
case CORTEX_M23:
t->core = "M23";
break;
case CORTEX_M3:
t->core = "M3";
break;
case CORTEX_M4:
t->core = "M4";
break;
case CORTEX_M7:
t->core = "M7";
if ((t->cpuid & CPUID_REVISION_MASK) == 0 && (t->cpuid & CPUID_PATCH_MASK) < 2)
DEBUG_WARN("Silicon bug: Single stepping will enter pending "
"exception handler with this M7 core revision!\n");
break;
case CORTEX_M0P:
t->core = "M0+";
break;
case CORTEX_M0:
t->core = "M0";
break;
default:
if (ap->designer_code != JEP106_MANUFACTURER_ATMEL) /* Protected Atmel device?*/
DEBUG_WARN("Unexpected Cortex-M CPU partno %04" PRIx32 "\n", cpuid_partno);
}
DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n", t->cpuid, t->core,
(t->cpuid & CPUID_REVISION_MASK) >> 20, t->cpuid & CPUID_PATCH_MASK);
}
bool cortexm_probe(ADIv5_AP_t *ap) bool cortexm_probe(ADIv5_AP_t *ap)
{ {
target *t; target *t;
@ -525,45 +567,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
t->driver = cortexm_driver_str; t->driver = cortexm_driver_str;
/* The CPUID register is defined in the ARMv7-M and ARMv8-M cortexm_read_cpuid(t, ap);
* architecture manuals. The PARTNO field is implementation defined,
* that is, the actual values are found in the Technical Reference Manual
* for each Cortex-M core.
*/
t->cpuid = target_mem_read32(t, CORTEXM_CPUID);
uint32_t cpuid_partno = t->cpuid & CPUID_PARTNO_MASK;
switch (cpuid_partno) {
case CORTEX_M33:
t->core = "M33";
break;
case CORTEX_M23:
t->core = "M23";
break;
case CORTEX_M3:
t->core = "M3";
break;
case CORTEX_M4:
t->core = "M4";
break;
case CORTEX_M7:
t->core = "M7";
if (((t->cpuid & CPUID_REVISION_MASK) == 0) && (t->cpuid & CPUID_PATCH_MASK) < 2) {
DEBUG_WARN("Silicon bug: Single stepping will enter pending "
"exception handler with this M7 core revision!\n");
}
break;
case CORTEX_M0P:
t->core = "M0+";
break;
case CORTEX_M0:
t->core = "M0";
break;
default:
if (ap->designer_code != JEP106_MANUFACTURER_ATMEL) /* Protected Atmel device?*/
DEBUG_WARN("Unexpected CortexM CPUID partno %04" PRIx32 "\n", cpuid_partno);
}
DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n", t->cpuid, t->core,
(t->cpuid & CPUID_REVISION_MASK) >> 20, t->cpuid & CPUID_PATCH_MASK);
t->attach = cortexm_attach; t->attach = cortexm_attach;
t->detach = cortexm_detach; t->detach = cortexm_detach;

17
src/target/cortexm.h
View File

@ -173,15 +173,14 @@ extern unsigned cortexm_wait_timeout;
#define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U) #define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U)
enum cortexm_types { #define CORTEX_M0 0xc200U
CORTEX_M0 = 0xc200, #define CORTEX_M0P 0xc600U
CORTEX_M0P = 0xc600, #define CORTEX_M3 0xc230U
CORTEX_M3 = 0xc230, #define CORTEX_M4 0xc240U
CORTEX_M4 = 0xc240, #define CORTEX_M7 0xc270U
CORTEX_M7 = 0xc270, #define CORTEX_M23 0xd200U
CORTEX_M23 = 0xd200, #define CORTEX_M33 0xd210U
CORTEX_M33 = 0xd210,
};
#define CPUID_PARTNO_MASK 0xfff0U #define CPUID_PARTNO_MASK 0xfff0U
#define CPUID_REVISION_MASK 0x00f00000U #define CPUID_REVISION_MASK 0x00f00000U
#define CPUID_PATCH_MASK 0xfU #define CPUID_PATCH_MASK 0xfU