Move STM32L[01] bit definitions to their driver and remove header.
This commit is contained in:
Gareth McMullin
parent
6b49fbe594
commit
0fc61efe7c
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@ -1,190 +0,0 @@
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/* @file stm32lx-nvm.h
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*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2014 Woollysoft
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* Written by Marc Singer <elf@woollysoft.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined (STM32Lx_NVM_H_INCLUDED)
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# define STM32Lx_NVM_H_INCLUDED
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/* ----- Includes */
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#include <stdint.h>
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/* ----- Macros */
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/* ----- Types */
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enum {
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STM32Lx_STUB_PHYS = 0x20000000ul,
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STM32Lx_STUB_INFO_PHYS = 0x20000004ul,
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STM32Lx_STUB_DATA_PHYS = (0x20000000ul + 1024),
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STM32Lx_STUB_DATA_MAX = 2048,
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STM32Lx_NVM_OPT_PHYS = 0x1ff80000ul,
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STM32Lx_NVM_EEPROM_PHYS = 0x08080000ul,
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STM32L0_NVM_PHYS = 0x40022000ul,
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STM32L0_NVM_PROG_PAGE_SIZE = 128,
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STM32L0_NVM_DATA_PAGE_SIZE = 4,
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STM32L0_NVM_OPT_SIZE = 12,
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STM32L0_NVM_EEPROM_SIZE = 2*1024,
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STM32L1_NVM_PHYS = 0x40023c00ul,
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STM32L1_NVM_PROG_PAGE_SIZE = 256,
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STM32L1_NVM_DATA_PAGE_SIZE = 4,
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STM32L1_NVM_OPT_SIZE = 32,
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STM32L1_NVM_EEPROM_SIZE = 16*1024,
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STM32Lx_NVM_PEKEY1 = 0x89abcdeful,
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STM32Lx_NVM_PEKEY2 = 0x02030405ul,
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STM32Lx_NVM_PRGKEY1 = 0x8c9daebful,
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STM32Lx_NVM_PRGKEY2 = 0x13141516ul,
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STM32Lx_NVM_OPTKEY1 = 0xfbead9c8ul,
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STM32Lx_NVM_OPTKEY2 = 0x24252627ul,
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STM32Lx_NVM_PECR_OBL_LAUNCH = (1<<18),
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STM32Lx_NVM_PECR_ERRIE = (1<<17),
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STM32Lx_NVM_PECR_EOPIE = (1<<16),
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STM32Lx_NVM_PECR_FPRG = (1<<10),
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STM32Lx_NVM_PECR_ERASE = (1<< 9),
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STM32Lx_NVM_PECR_FIX = (1<< 8), /* FTDW */
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STM32Lx_NVM_PECR_DATA = (1<< 4),
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STM32Lx_NVM_PECR_PROG = (1<< 3),
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STM32Lx_NVM_PECR_OPTLOCK = (1<< 2),
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STM32Lx_NVM_PECR_PRGLOCK = (1<< 1),
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STM32Lx_NVM_PECR_PELOCK = (1<< 0),
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STM32Lx_NVM_SR_FWWERR = (1<<17),
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STM32Lx_NVM_SR_NOTZEROERR = (1<<16),
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STM32Lx_NVM_SR_RDERR = (1<<13),
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STM32Lx_NVM_SR_OPTVER = (1<<11),
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STM32Lx_NVM_SR_SIZERR = (1<<10),
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STM32Lx_NVM_SR_PGAERR = (1<<9),
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STM32Lx_NVM_SR_WRPERR = (1<<8),
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STM32Lx_NVM_SR_READY = (1<<3),
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STM32Lx_NVM_SR_HWOFF = (1<<2),
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STM32Lx_NVM_SR_EOP = (1<<1),
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STM32Lx_NVM_SR_BSY = (1<<0),
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STM32Lx_NVM_SR_ERR_M = ( STM32Lx_NVM_SR_WRPERR
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| STM32Lx_NVM_SR_PGAERR
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| STM32Lx_NVM_SR_SIZERR
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| STM32Lx_NVM_SR_NOTZEROERR),
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STM32L0_NVM_OPTR_BOOT1 = (1<<31),
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STM32L0_NVM_OPTR_WDG_SW = (1<<20),
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STM32L0_NVM_OPTR_WPRMOD = (1<<8),
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STM32L0_NVM_OPTR_RDPROT_S = (0),
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STM32L0_NVM_OPTR_RDPROT_M = (0xff),
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STM32L0_NVM_OPTR_RDPROT_0 = (0xaa),
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STM32L0_NVM_OPTR_RDPROT_2 = (0xcc),
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STM32L1_NVM_OPTR_nBFB2 = (1<<23),
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STM32L1_NVM_OPTR_nRST_STDBY = (1<<22),
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STM32L1_NVM_OPTR_nRST_STOP = (1<<21),
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STM32L1_NVM_OPTR_WDG_SW = (1<<20),
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STM32L1_NVM_OPTR_BOR_LEV_S = (16),
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STM32L1_NVM_OPTR_BOR_LEV_M = (0xf),
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STM32L1_NVM_OPTR_SPRMOD = (1<<8),
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STM32L1_NVM_OPTR_RDPROT_S = (0),
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STM32L1_NVM_OPTR_RDPROT_M = (0xff),
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STM32L1_NVM_OPTR_RDPROT_0 = (0xaa),
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STM32L1_NVM_OPTR_RDPROT_2 = (0xcc),
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};
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#if defined (__cplusplus)
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namespace STM32 {
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struct NVM {
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volatile uint32_t acr;
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volatile uint32_t pecr;
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volatile uint32_t pdkeyr;
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volatile uint32_t pkeyr;
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volatile uint32_t prgkeyr;
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volatile uint32_t optkeyr;
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volatile uint32_t sr;
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volatile uint32_t optr;
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volatile uint32_t wrprot;
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static constexpr uint32_t PKEY1 = 0x89abcdef;
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static constexpr uint32_t PKEY2 = 0x02030405;
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static constexpr uint32_t PRGKEY1 = 0x8c9daebf;
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static constexpr uint32_t PRGKEY2 = 0x13141516;
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static constexpr uint32_t OPTKEY1 = 0xfbead9c8;
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static constexpr uint32_t OPTKEY2 = 0x24252627;
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static constexpr uint32_t PDKEY1 = 0x04152637;
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static constexpr uint32_t PDKEY2 = 0xfafbfcfd;
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};
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static_assert(sizeof (NVM) == 9*4, "NVM size error");
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}
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using stm32lx_stub_pointer_t = uint32_t*;
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#define Nvm(nvm) (*reinterpret_cast<STM32::NVM*>(nvm))
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#define Info (*reinterpret_cast<stm32lx_nvm_stub_info*>(STM32Lx_STUB_INFO_PHYS))
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namespace {
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inline __attribute((always_inline)) bool unlock (STM32::NVM& nvm) {
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// Lock guarantees unlock
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nvm.pecr = STM32Lx_NVM_PECR_PELOCK;
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nvm.pkeyr = STM32::NVM::PKEY1;
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nvm.pkeyr = STM32::NVM::PKEY2;
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nvm.prgkeyr = STM32::NVM::PRGKEY1;
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nvm.prgkeyr = STM32::NVM::PRGKEY2;
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return !(nvm.pecr & STM32Lx_NVM_PECR_PRGLOCK);
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}
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inline __attribute((always_inline)) void lock (STM32::NVM& nvm) {
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nvm.pecr = STM32Lx_NVM_PECR_PELOCK; }
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}
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#else
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typedef uint32_t stm32lx_stub_pointer_t;
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#define STM32Lx_NVM_PECR(p) ((p) + 0x04)
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#define STM32Lx_NVM_PEKEYR(p) ((p) + 0x0C)
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#define STM32Lx_NVM_PRGKEYR(p) ((p) + 0x10)
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#define STM32Lx_NVM_OPTKEYR(p) ((p) + 0x14)
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#define STM32Lx_NVM_SR(p) ((p) + 0x18)
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#define STM32Lx_NVM_OPTR(p) ((p) + 0x1C)
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#endif
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enum {
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OPT_STM32L1 = 1<<1,
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};
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struct stm32lx_nvm_stub_info {
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stm32lx_stub_pointer_t destination;
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int32_t size;
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stm32lx_stub_pointer_t source;
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uint32_t nvm;
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uint16_t page_size;
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uint16_t options;
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} __attribute__((packed));
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/* ----- Globals */
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/* ----- Prototypes */
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#endif /* STM32Lx_NVM_H_INCLUDED */
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@ -80,7 +80,68 @@
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#include "gdb_packet.h"
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#include "cortexm.h"
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#include "stm32lx-nvm.h"
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#define STM32Lx_NVM_PECR(p) ((p) + 0x04)
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#define STM32Lx_NVM_PEKEYR(p) ((p) + 0x0C)
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#define STM32Lx_NVM_PRGKEYR(p) ((p) + 0x10)
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#define STM32Lx_NVM_OPTKEYR(p) ((p) + 0x14)
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#define STM32Lx_NVM_SR(p) ((p) + 0x18)
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#define STM32Lx_NVM_OPTR(p) ((p) + 0x1C)
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#define STM32L0_NVM_PHYS (0x40022000ul)
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#define STM32L0_NVM_OPT_SIZE (12)
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#define STM32L0_NVM_EEPROM_SIZE (2*1024)
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#define STM32L1_NVM_PHYS (0x40023c00ul)
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#define STM32L1_NVM_OPT_SIZE (32)
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#define STM32L1_NVM_EEPROM_SIZE (16*1024)
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#define STM32Lx_NVM_OPT_PHYS 0x1ff80000ul
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#define STM32Lx_NVM_EEPROM_PHYS 0x08080000ul
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#define STM32Lx_NVM_PEKEY1 (0x89abcdeful)
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#define STM32Lx_NVM_PEKEY2 (0x02030405ul)
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#define STM32Lx_NVM_PRGKEY1 (0x8c9daebful)
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#define STM32Lx_NVM_PRGKEY2 (0x13141516ul)
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#define STM32Lx_NVM_OPTKEY1 (0xfbead9c8ul)
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#define STM32Lx_NVM_OPTKEY2 (0x24252627ul)
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#define STM32Lx_NVM_PECR_OBL_LAUNCH (1<<18)
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#define STM32Lx_NVM_PECR_ERRIE (1<<17)
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#define STM32Lx_NVM_PECR_EOPIE (1<<16)
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#define STM32Lx_NVM_PECR_FPRG (1<<10)
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#define STM32Lx_NVM_PECR_ERASE (1<< 9)
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#define STM32Lx_NVM_PECR_FIX (1<< 8) /* FTDW */
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#define STM32Lx_NVM_PECR_DATA (1<< 4)
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#define STM32Lx_NVM_PECR_PROG (1<< 3)
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#define STM32Lx_NVM_PECR_OPTLOCK (1<< 2)
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#define STM32Lx_NVM_PECR_PRGLOCK (1<< 1)
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#define STM32Lx_NVM_PECR_PELOCK (1<< 0)
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#define STM32Lx_NVM_SR_NOTZEROERR (1<<16)
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#define STM32Lx_NVM_SR_SIZERR (1<<10)
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#define STM32Lx_NVM_SR_PGAERR (1<<9)
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#define STM32Lx_NVM_SR_WRPERR (1<<8)
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#define STM32Lx_NVM_SR_EOP (1<<1)
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#define STM32Lx_NVM_SR_BSY (1<<0)
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#define STM32Lx_NVM_SR_ERR_M (STM32Lx_NVM_SR_WRPERR | \
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STM32Lx_NVM_SR_PGAERR | \
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STM32Lx_NVM_SR_SIZERR | \
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STM32Lx_NVM_SR_NOTZEROERR)
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#define STM32L0_NVM_OPTR_BOOT1 (1<<31)
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#define STM32Lx_NVM_OPTR_WDG_SW (1<<20)
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#define STM32L0_NVM_OPTR_WPRMOD (1<<8)
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#define STM32Lx_NVM_OPTR_RDPROT_S (0)
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#define STM32Lx_NVM_OPTR_RDPROT_M (0xff)
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#define STM32Lx_NVM_OPTR_RDPROT_0 (0xaa)
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#define STM32Lx_NVM_OPTR_RDPROT_2 (0xcc)
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#define STM32L1_NVM_OPTR_nBFB2 (1<<23)
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#define STM32L1_NVM_OPTR_nRST_STDBY (1<<22)
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#define STM32L1_NVM_OPTR_nRST_STOP (1<<21)
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#define STM32L1_NVM_OPTR_BOR_LEV_S (16)
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#define STM32L1_NVM_OPTR_BOR_LEV_M (0xf)
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#define STM32L1_NVM_OPTR_SPRMOD (1<<8)
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static int stm32lx_nvm_prog_erase(struct target_flash* f,
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uint32_t addr, size_t len);
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@ -566,11 +627,11 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv)
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if (stm32lx_is_stm32l1(t)) {
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uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm));
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uint8_t rdprot = (optr >> STM32L1_NVM_OPTR_RDPROT_S)
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& STM32L1_NVM_OPTR_RDPROT_M;
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if (rdprot == STM32L1_NVM_OPTR_RDPROT_0)
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uint8_t rdprot = (optr >> STM32Lx_NVM_OPTR_RDPROT_S)
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& STM32Lx_NVM_OPTR_RDPROT_M;
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if (rdprot == STM32Lx_NVM_OPTR_RDPROT_0)
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rdprot = 0;
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else if (rdprot == STM32L1_NVM_OPTR_RDPROT_2)
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else if (rdprot == STM32Lx_NVM_OPTR_RDPROT_2)
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rdprot = 2;
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else
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rdprot = 1;
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@ -581,18 +642,18 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv)
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(optr & STM32L1_NVM_OPTR_SPRMOD) ? 1 : 0,
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(optr >> STM32L1_NVM_OPTR_BOR_LEV_S)
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& STM32L1_NVM_OPTR_BOR_LEV_M,
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(optr & STM32L1_NVM_OPTR_WDG_SW) ? 1 : 0,
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(optr & STM32Lx_NVM_OPTR_WDG_SW) ? 1 : 0,
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(optr & STM32L1_NVM_OPTR_nRST_STOP) ? 1 : 0,
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(optr & STM32L1_NVM_OPTR_nRST_STDBY) ? 1 : 0,
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(optr & STM32L1_NVM_OPTR_nBFB2) ? 1 : 0);
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}
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else {
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uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm));
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uint8_t rdprot = (optr >> STM32L0_NVM_OPTR_RDPROT_S)
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& STM32L0_NVM_OPTR_RDPROT_M;
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if (rdprot == STM32L0_NVM_OPTR_RDPROT_0)
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uint8_t rdprot = (optr >> STM32Lx_NVM_OPTR_RDPROT_S)
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& STM32Lx_NVM_OPTR_RDPROT_M;
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if (rdprot == STM32Lx_NVM_OPTR_RDPROT_0)
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rdprot = 0;
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else if (rdprot == STM32L0_NVM_OPTR_RDPROT_2)
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else if (rdprot == STM32Lx_NVM_OPTR_RDPROT_2)
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rdprot = 2;
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else
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rdprot = 1;
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@ -600,7 +661,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv)
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"BOOT1 %d\n",
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optr, rdprot,
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(optr & STM32L0_NVM_OPTR_WPRMOD) ? 1 : 0,
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(optr & STM32L0_NVM_OPTR_WDG_SW) ? 1 : 0,
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(optr & STM32Lx_NVM_OPTR_WDG_SW) ? 1 : 0,
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(optr & STM32L0_NVM_OPTR_BOOT1) ? 1 : 0);
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}
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