cortexm: Fix protected SAM detection
- Only run cortex_prepare() if reading cidr fails - With Atmel DSU detected, run cortexm_probe()
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@ -409,6 +409,15 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
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if (addr == 0) /* No rom table on this AP */
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return false;
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uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
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if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
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/* Maybe caused by a not halted CortexM */
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if (!ap->apsel && ((ap->idr & 0xf) == ARM_AP_TYPE_AHB)) {
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if (!cortexm_prepare(ap))
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return false; /* Halting failed! */
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/* CPU now halted, read cidr again. */
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cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
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}
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}
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bool res = false;
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#if defined(ENABLE_DEBUG)
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char indent[recursion + 1];
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@ -454,6 +463,10 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
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if (recursion == 0) {
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ap->ap_designer = designer;
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ap->ap_partno = partno;
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if ((ap->ap_designer == AP_DESIGNER_ATMEL) && (ap->ap_partno == 0xcd0)) {
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cortexm_probe(ap);
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return true;
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}
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}
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for (int i = 0; i < 960; i++) {
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adiv5_dp_error(ap->dp);
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@ -598,25 +611,6 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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DEBUG_INFO("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08" PRIx32
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" CSW=%08"PRIx32"\n", apsel, ap->idr, cfg, ap->base, ap->csw);
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#endif
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if (!apsel && ((ap->idr & 0xf) == ARM_AP_TYPE_AHB)) {
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/* Test for protected Atmel devices. Access outside DSU fails.
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* For protected device, continue with Rom Table anyways.
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*/
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adiv5_dp_error(ap->dp);
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adiv5_mem_read32(ap, CORTEXM_DHCSR);
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if ( adiv5_dp_error(ap->dp) & ADIV5_DP_CTRLSTAT_STICKYERR) {
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uint32_t err = adiv5_dp_error(ap->dp);
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if (err & ADIV5_DP_CTRLSTAT_STICKYERR) {
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DEBUG_WARN("...\nHit error on DHCSR read. Suspect protected Atmel "
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"part, skipping to PIDR check.\n");
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}
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} else {
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if (!cortexm_prepare(ap)) {
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free(ap);
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return NULL;
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}
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}
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}
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adiv5_ap_ref(ap);
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return ap;
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}
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