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target/adi: correct raspberry jep code, cleanup dpidr/targetid code handling

This commit is contained in:
Rafael Silva 2022-07-28 17:07:20 +01:00 committed by Rachel Mant
parent 58025feec2
commit 1286faff64
4 changed files with 57 additions and 15 deletions
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29
src/target/adiv5.c
View File

@ -682,25 +682,36 @@ static void rp_rescue_setup(ADIv5_DP_t *dp)
void adiv5_dp_init(ADIv5_DP_t *dp)
{
/*
* the code in the DPIDR is in the form
* Bits 10:7 - JEP-106 Continuation code
* Bits 6:0 - JEP-106 Identity code
* here we convert it to our internal representation, See JEP-106 code list
* note, this is the code of the designer not the implementer, we expect it to be ARM
*/
const uint16_t designer = (dp->debug_port_id & ADIV5_DP_DPIDR_DESIGNER_MASK) >> ADIV5_DP_DPIDR_DESIGNER_OFFSET;
dp->designer_code = (designer & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
(designer & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
dp->partno = (dp->debug_port_id & ADIV5_DP_DPIDR_PARTNO_MASK) >> ADIV5_DP_DPIDR_PARTNO_OFFSET;
/* Check DPIDR for a valid manufacturer and sensible PARTNO */
if ((dp->debug_port_id & ADIV5_DP_DPIDR_DESIGNER_MASK) == 0 ||
(dp->debug_port_id & ADIV5_DP_DPIDR_PARTNO_MASK) == ADIV5_DP_DPIDR_PARTNO_MASK) {
if (dp->designer_code == 0 || dp->partno == 0xff7fU) {
DEBUG_WARN("Invalid DP DPIDR %08" PRIx32 "\n", dp->debug_port_id);
free(dp);
return;
}
/* TODO: this could with a non 'magic number' */
if (dp->debug_port_id == 0x10212927) {
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d) designer 0x%" PRIx32 " partno 0x%" PRIx32 "\n", dp->debug_port_id,
(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET),
(dp->debug_port_id & ADIV5_DP_DPIDR_MINDP) ? "MINDP " : "",
(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET), dp->designer_code,
dp->partno);
if (dp->designer_code == JEP106_MANUFACTURER_RASPBERRY && dp->partno == 0x2) {
rp_rescue_setup(dp);
return;
}
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->debug_port_id,
(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET),
(dp->debug_port_id & ADIV5_DP_DPIDR_MINDP) ? "MINDP " : "",
(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET));
#if PC_HOSTED == 1
platform_adiv5_dp_defaults(dp);
if (!dp->ap_write)

23
src/target/adiv5.h
View File

@ -46,7 +46,7 @@
#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xCU)
#define ADIV5_DP_TARGETSEL ADIV5_DP_REG(0xCU)
/* AP DPIDR */
/* DP DPIDR */
#define ADIV5_DP_DPIDR_REVISION_OFFSET 28U
#define ADIV5_DP_DPIDR_REVISION_MASK (0xfU << ADIV5_DP_DPIDR_VERSION_OFFSET)
#define ADIV5_DP_DPIDR_PARTNO_OFFSET 20U
@ -60,6 +60,21 @@
#define ADIV5_DP_DPIDR_DESIGNER_OFFSET 1U
#define ADIV5_DP_DPIDR_DESIGNER_MASK (0x7ffU << ADIV5_DP_DPIDR_DESIGNER_OFFSET)
/* DP TARGETID */
#define ADIV5_DP_TARGETID_TREVISION_OFFSET 28U
#define ADIV5_DP_TARGETID_TREVISION_MASK (0xfU << ADIV5_DP_TARGETID_TREVISION_OFFSET)
#define ADIV5_DP_TARGETID_TPARTNO_OFFSET 12U
#define ADIV5_DP_TARGETID_TPARTNO_MASK (0xffffU << ADIV5_DP_TARGETID_TPARTNO_OFFSET)
#define ADIV5_DP_TARGETID_TDESIGNER_OFFSET 1U
#define ADIV5_DP_TARGETID_TDESIGNER_MASK (0x7ffU << ADIV5_DP_TARGETID_TDESIGNER_OFFSET)
/* DP DPIDR/TARGETID DESIGNER */
/* Bits 10:7 - JEP-106 Continuation code */
/* Bits 6:0 - JEP-106 Identity code */
#define ADIV5_DP_DESIGNER_JEP106_CONT_OFFSET 7U
#define ADIV5_DP_DESIGNER_JEP106_CONT_MASK (0xfU << ADIV5_DP_DESIGNER_JEP106_CONT_OFFSET)
#define ADIV5_DP_DESIGNER_JEP106_CODE_MASK (0x7fU)
/* AP Abort Register (ABORT) */
/* Bits 31:5 - Reserved */
#define ADIV5_DP_ABORT_ORUNERRCLR (1U << 4U)
@ -167,7 +182,7 @@
#define JEP106_MANUFACTURER_SPECULAR 0x501U /* LPC845 with code 501. Strange!? Specular Networks */
#define JEP106_MANUFACTURER_ENERGY_MICRO 0x673U /* Energy Micro */
#define JEP106_MANUFACTURER_GIGADEVICE 0x751U /* GigaDevice */
#define JEP106_MANUFACTURER_RASPBERRY 0x927U /* Raspberry Pi */
#define JEP106_MANUFACTURER_RASPBERRY 0x913U /* Raspberry Pi */
/*
* This code is not listed in the JEP106 standard, but is used by some stm32f1 clones
@ -205,6 +220,10 @@ typedef struct ADIv5_DP_s {
int refcnt;
uint32_t debug_port_id;
uint16_t designer_code;
uint16_t partno;
uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
void (*seq_out)(uint32_t tms_states, size_t clock_cycles);

13
src/target/adiv5_swdp.c
View File

@ -128,12 +128,19 @@ int adiv5_swdp_scan(uint32_t targetid)
target_id = adiv5_dp_read(initial_dp, ADIV5_DP_CTRLSTAT);
adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 0);
DEBUG_INFO("TARGETID %08" PRIx32 "\n", target_id);
switch (target_id) {
case 0x01002927: /* RP2040 */
const uint16_t tdesigner =
(target_id & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
const uint16_t tpartno = (target_id & ADIV5_DP_TARGETID_TPARTNO_MASK) >> ADIV5_DP_TARGETID_TPARTNO_OFFSET;
/* convert it to our internal representation, See JEP-106 code list */
const uint16_t designer_code = (tdesigner & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
(tdesigner & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
if (designer_code == JEP106_MANUFACTURER_RASPBERRY && tpartno == 0x2) {
/* RP2040 */
/* Release evt. handing RESCUE DP reset*/
adiv5_dp_write(initial_dp, ADIV5_DP_CTRLSTAT, 0);
break;
}
if (!initial_dp->dp_low_write) {
DEBUG_WARN("CMSIS_DAP < V1.2 can not handle multi-drop!\n");
/* E.g. CMSIS_DAP < V1.2 can not handle multi-drop!*/

7
src/target/cortexm.c
View File

@ -456,7 +456,12 @@ bool cortexm_probe(ADIv5_AP_t *ap)
#endif
}
if (ap->ap_partno == 0x4c0) { /* Cortex-M0+ ROM */
if ((ap->dp->targetid & 0xfff) == JEP106_MANUFACTURER_RASPBERRY)
const uint16_t tdesigner =
(ap->dp->targetid & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
/* convert it to our internal representation, See JEP-106 code list */
const uint16_t designer_code = (tdesigner & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
(tdesigner & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
if (designer_code == JEP106_MANUFACTURER_RASPBERRY)
PROBE(rp_probe);
PROBE(lpc11xx_probe); /* LPC8 */
} else if (ap->ap_partno == 0x4c3) { /* Cortex-M3 ROM */