cortexm: Allow to set timeout to wait for halt.

This allows to gain access to devices spending long time in WFI without
the need for a reset, at the expense of possible long waiting times.
Using Reset means loosing the device runtime context.

src/command.c

@@ -57,6 +57,7 @@ static bool cmd_swdp_scan(void);
 static bool cmd_targets(void);
 static bool cmd_morse(void);
 static bool cmd_assert_srst(target *t, int argc, const char **argv);
+static bool cmd_halt_timeout(target *t, int argc, const char **argv);
 static bool cmd_hard_srst(void);
 #ifdef PLATFORM_HAS_POWER_SWITCH
 static bool cmd_target_power(target *t, int argc, const char **argv);
@@ -76,6 +77,7 @@ const struct command_s cmd_list[] = {
 	{"targets", (cmd_handler)cmd_targets, "Display list of available targets" },
 	{"morse", (cmd_handler)cmd_morse, "Display morse error message" },
 	{"assert_srst", (cmd_handler)cmd_assert_srst, "Assert SRST until:(never(default)| scan | attach)" },
+	{"halt_timeout", (cmd_handler)cmd_halt_timeout, "Timeout (ms) to wait until Cortex-M is halted: (Default 2000)" },
 	{"hard_srst", (cmd_handler)cmd_hard_srst, "Force a pulse on the hard SRST line - disconnects target" },
 #ifdef PLATFORM_HAS_POWER_SWITCH
 	{"tpwr", (cmd_handler)cmd_target_power, "Supplies power to the target: (enable|disable)"},
@@ -93,6 +95,7 @@ static enum assert_srst_t assert_srst;
 #ifdef PLATFORM_HAS_DEBUG
 bool debug_bmp;
 #endif
+long cortexm_wait_timeout = 2000; /* Timeout to wait for Cortex to react on halt command. */
 
 int command_process(target *t, char *cmd)
 {
@@ -271,6 +274,16 @@ static bool cmd_assert_srst(target *t, int argc, const char **argv)
 	return true;
 }
 
+static bool cmd_halt_timeout(target *t, int argc, const char **argv)
+{
+	(void)t;
+	if (argc > 1)
+		cortexm_wait_timeout = atol(argv[1]);
+	gdb_outf("Cortex-M timeout to wait for device haltes: %d\n",
+				 cortexm_wait_timeout);
+	return true;
+}
+
 static bool cmd_hard_srst(void)
 {
 	target_list_free();

src/target/cortexm.c

@@ -252,7 +252,7 @@ static bool cortexm_forced_halt(target *t)
 	start_time = platform_time_ms();
 	/* Try hard to halt the target. STM32F7 in  WFI
 	   needs multiple writes!*/
-	while (platform_time_ms() < start_time + 2000) {
+	while (platform_time_ms() < start_time + cortexm_wait_timeout) {
 		dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
 		if (dhcsr == (CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_S_REGRDY |
 					  CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN))

src/target/cortexm.h

@@ -22,6 +22,7 @@
 #include "target.h"
 #include "adiv5.h"
 
+extern long cortexm_wait_timeout;
 /* Private peripheral bus base address */
 #define CORTEXM_PPB_BASE	0xE0000000