adiv5: Rework DP/AP refcounting.
ASAN non longer reports leaks with the STM32H745.
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f76a7c4e92
commit
18673d9a56
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@ -352,7 +352,6 @@ int platform_adiv5_swdp_scan(void)
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if (target_list)
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if (target_list)
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return 1;
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return 1;
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}
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}
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free(dp);
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break;
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break;
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}
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}
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case BMP_TYPE_CMSIS_DAP:
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case BMP_TYPE_CMSIS_DAP:
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@ -364,7 +363,6 @@ int platform_adiv5_swdp_scan(void)
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if (target_list)
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if (target_list)
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return 1;
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return 1;
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}
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}
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free(dp);
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break;
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break;
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}
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}
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case BMP_TYPE_JLINK:
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case BMP_TYPE_JLINK:
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@ -494,5 +494,6 @@ int cl_execute(BMP_CL_OPTIONS_t *opt)
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target_detach:
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target_detach:
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if (t)
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if (t)
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target_detach(t);
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target_detach(t);
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target_list_free();
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return res;
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return res;
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}
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}
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@ -263,13 +263,10 @@ static const struct {
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extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
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extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
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static void adiv5_dp_ref(ADIv5_DP_t *dp)
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{
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dp->refcnt++;
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}
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void adiv5_ap_ref(ADIv5_AP_t *ap)
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void adiv5_ap_ref(ADIv5_AP_t *ap)
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{
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{
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if (ap->refcnt == 0)
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ap->dp->refcnt++;
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ap->refcnt++;
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ap->refcnt++;
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}
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}
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@ -404,6 +401,7 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
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return true;
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return true;
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}
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}
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/* Return true if we find a debuggable device.*/
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static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
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static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
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{
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{
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(void) num_entry;
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(void) num_entry;
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@ -488,7 +486,7 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
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}
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}
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/* Probe recursively */
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/* Probe recursively */
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adiv5_component_probe(
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res = adiv5_component_probe(
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ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET),
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ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET),
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recursion + 1, i);
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recursion + 1, i);
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}
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}
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@ -543,15 +541,14 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
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cidc_debug_strings[cid_class],
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cidc_debug_strings[cid_class],
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cidc_debug_strings[pidr_pn_bits[i].cidc]);
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cidc_debug_strings[pidr_pn_bits[i].cidc]);
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}
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}
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res = true;
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switch (pidr_pn_bits[i].arch) {
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switch (pidr_pn_bits[i].arch) {
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case aa_cortexm:
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case aa_cortexm:
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DEBUG_INFO("%s-> cortexm_probe\n", indent + 1);
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DEBUG_INFO("%s-> cortexm_probe\n", indent + 1);
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cortexm_probe(ap);
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res = cortexm_probe(ap);
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break;
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break;
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case aa_cortexa:
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case aa_cortexa:
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DEBUG_INFO("\n -> cortexa_probe\n");
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DEBUG_INFO("\n -> cortexa_probe\n");
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cortexa_probe(ap, addr);
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res = cortexa_probe(ap, addr);
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break;
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break;
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default:
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default:
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DEBUG_INFO("\n");
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DEBUG_INFO("\n");
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@ -598,7 +595,6 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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}
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}
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memcpy(ap, &tmpap, sizeof(*ap));
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memcpy(ap, &tmpap, sizeof(*ap));
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adiv5_dp_ref(dp);
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ap->csw = adiv5_ap_read(ap, ADIV5_AP_CSW) &
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ap->csw = adiv5_ap_read(ap, ADIV5_AP_CSW) &
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~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
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~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
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@ -620,7 +616,6 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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void adiv5_dp_init(ADIv5_DP_t *dp)
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void adiv5_dp_init(ADIv5_DP_t *dp)
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{
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{
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volatile uint32_t ctrlstat = 0;
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volatile uint32_t ctrlstat = 0;
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adiv5_dp_ref(dp);
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#if PC_HOSTED == 1
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#if PC_HOSTED == 1
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platform_adiv5_dp_defaults(dp);
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platform_adiv5_dp_defaults(dp);
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if (!dp->ap_write)
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if (!dp->ap_write)
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@ -693,6 +688,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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}
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}
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}
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}
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bool res = false;
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uint32_t dp_idcode = adiv5_dp_read(dp, ADIV5_DP_IDCODE);
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uint32_t dp_idcode = adiv5_dp_read(dp, ADIV5_DP_IDCODE);
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if ((dp_idcode & ADIV5_DP_VERSION_MASK) == ADIV5_DPv2) {
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if ((dp_idcode & ADIV5_DP_VERSION_MASK) == ADIV5_DPv2) {
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/* Read TargetID. Can be done with device in WFI, sleep or reset!*/
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/* Read TargetID. Can be done with device in WFI, sleep or reset!*/
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@ -729,7 +725,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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if (dp->ap_cleanup)
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if (dp->ap_cleanup)
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dp->ap_cleanup(i);
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dp->ap_cleanup(i);
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#endif
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#endif
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free(ap);
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adiv5_ap_unref(ap);
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/* FIXME: Should we expect valid APs behind duplicate ones? */
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/* FIXME: Should we expect valid APs behind duplicate ones? */
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return;
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return;
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}
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}
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@ -748,13 +744,14 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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*/
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*/
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/* The rest should only be added after checking ROM table */
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/* The rest should only be added after checking ROM table */
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adiv5_component_probe(ap, ap->base, 0, 0);
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res = adiv5_component_probe(ap, ap->base, 0, 0);
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if (!res)
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adiv5_ap_unref(ap);
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}
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}
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/* We halted at least CortexM for Romtable scan.
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/* We halted at least CortexM for Romtable scan.
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* Release the devices now. Attach() will halt them again.*/
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* Release the devices now. Attach() will halt them again.*/
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for (target *t = target_list; t; t = t->next)
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for (target *t = target_list; t; t = t->next)
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target_halt_resume(t, false);
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target_halt_resume(t, false);
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adiv5_dp_unref(dp);
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}
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}
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#define ALIGNOF(x) (((x) & 3) == 0 ? ALIGN_WORD : \
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#define ALIGNOF(x) (((x) & 3) == 0 ? ALIGN_WORD : \
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@ -38,21 +38,12 @@ int adiv5_swdp_scan(void)
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uint32_t ack;
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uint32_t ack;
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target_list_free();
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target_list_free();
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ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp));
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dp->dp_jd_index = JTAG_MAX_DEVS; /* Tag for BMP_REMOTE */
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if (!dp) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return -1;
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}
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#if PC_HOSTED == 1
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#if PC_HOSTED == 1
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if (platform_swdptap_init()) {
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if (platform_swdptap_init()) {
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free(dp);
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exit(-1);
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exit(-1);
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}
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}
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#else
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#else
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if (swdptap_init()) {
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if (swdptap_init()) {
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free(dp);
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return -1;
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return -1;
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}
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}
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#endif
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#endif
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@ -71,12 +62,19 @@ int adiv5_swdp_scan(void)
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* allow the ack to be checked here. */
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* allow the ack to be checked here. */
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swd_proc.swdptap_seq_out(0xA5, 8);
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swd_proc.swdptap_seq_out(0xA5, 8);
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ack = swd_proc.swdptap_seq_in(3);
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ack = swd_proc.swdptap_seq_in(3);
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if((ack != SWDP_ACK_OK) || swd_proc.swdptap_seq_in_parity(&dp->idcode, 32)) {
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uint32_t idcode;
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if((ack != SWDP_ACK_OK) || swd_proc.swdptap_seq_in_parity(&idcode, 32)) {
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DEBUG_WARN("Read SW-DP IDCODE failed %1" PRIx32 "\n", ack);
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DEBUG_WARN("Read SW-DP IDCODE failed %1" PRIx32 "\n", ack);
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free(dp);
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return -1;
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return -1;
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}
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}
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ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp));
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if (!dp) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return -1;
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}
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dp->idcode = idcode;
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dp->dp_read = firmware_swdp_read;
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dp->dp_read = firmware_swdp_read;
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dp->error = firmware_swdp_error;
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dp->error = firmware_swdp_error;
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dp->low_access = firmware_swdp_low_access;
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dp->low_access = firmware_swdp_low_access;
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@ -84,8 +82,6 @@ int adiv5_swdp_scan(void)
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firmware_swdp_error(dp);
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firmware_swdp_error(dp);
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adiv5_dp_init(dp);
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adiv5_dp_init(dp);
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if (!target_list)
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free(dp);
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return target_list?1:0;
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return target_list?1:0;
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}
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}
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