Merge pull request #139 from esden/pid_cid_tables
Use Product ID and Componend ID tables instead of defines.
This commit is contained in:
Gareth McMullin
GitHub
commit
1f9fbd2d0e
266
src/adiv5.c
266
src/adiv5.c
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@ -32,16 +32,181 @@
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#define DO_RESET_SEQ 0
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#endif
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/* ROM table CIDR values */
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#define CIDR_ROM_TABLE 0xb105100d
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#define CIDR_GENERIC_IP 0xb105e00d
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#define CIDR_DEBUG 0xb105900d
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/* All this should probably be defined in a dedicated ADIV5 header, so that they
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* are consistently named and accessible when needed in the codebase.
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*/
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#define PIDR_REV_MASK 0x0FFF00000ULL
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#define PIDR_ARMv7M 0x4000BB000ULL
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#define PIDR_ARMv6M 0x4000BB008ULL
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#define PIDR_ARMv7MF 0x4000BB00CULL
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#define PIDR_ARMv7A 0x4000BBC09ULL
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/* ROM table CIDR values */
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#define CIDR0_OFFSET 0xFF0 /* DBGCID0 */
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#define CIDR1_OFFSET 0xFF4 /* DBGCID1 */
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#define CIDR2_OFFSET 0xFF8 /* DBGCID2 */
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#define CIDR3_OFFSET 0xFFC /* DBGCID3 */
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/* Component class ID register can be broken down into the following logical
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* interpretation of the 32bit value consisting of the least significant bytes
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* of the 4 CID registers:
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* |7 ID3 reg 0|7 ID2 reg 0|7 ID1 reg 0|7 ID0 reg 0|
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* |1|0|1|1|0|0|0|1|0|0|0|0|0|1|0|1| | | | |0|0|0|0|0|0|0|0|1|1|0|1|
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* |31 24|23 16|15 12|11 | 0|
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* \_______________ ______________/\___ __/\___________ ___________/
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* V V V
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* Preamble Component Preamble
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* Class
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* \_______________________________ _______________________________/
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* V
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* Component ID
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*/
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#define CID_PREAMBLE 0xB105000D
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#define CID_CLASS_MASK 0x0000F000
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#define CID_CLASS_SHIFT 12
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/* The following enum is based on the Component Class value table 13-3 of the
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* ADIv5 standard.
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*/
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enum cid_class {
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cidc_gvc = 0x0, /* Generic verification component*/
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cidc_romtab = 0x1, /* ROM Table, std. layout (ADIv5 Chapter 14) */
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/* 0x2 - 0x8 */ /* Reserved */
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cidc_dc = 0x9, /* Debug component, std. layout (CoreSight Arch. Spec.) */
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/* 0xA */ /* Reserved */
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cidc_ptb = 0xB, /* Peripheral Test Block (PTB) */
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/* 0xC */ /* Reserved */
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cidc_dess = 0xD, /* OptimoDE Data Engine SubSystem (DESS) component */
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cidc_gipc = 0xE, /* Generic IP Component */
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cidc_pcp = 0xF, /* PrimeCell peripheral */
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cidc_unknown = 0x10
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};
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#ifdef PLATFORM_HAS_DEBUG
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/* The reserved ones only have an R in them, to save a bit of space. */
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static const char const *cidc_debug_strings[] =
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{
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[cidc_gvc] = "Generic verification component", /* 0x0 */
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[cidc_romtab] = "ROM Table", /* 0x1 */
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[0x2 ... 0x8] = "R", /* 0x2 - 0x8 */
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[cidc_dc] = "Debug component", /* 0x9 */
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[0xA] = "R", /* 0xA */
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[cidc_ptb] = "Peripheral Test Block", /* 0xB */
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[0xC] = "R", /* 0xC */
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[cidc_dess] = "OptimoDE Data Engine SubSystem component", /* 0xD */
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[cidc_gipc] = "Generic IP component", /* 0xE */
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[cidc_pcp] = "PrimeCell peripheral", /* 0xF */
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[cidc_unknown] = "Unknown component class" /* 0x10 */
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};
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#endif
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#define PIDR0_OFFSET 0xFE0 /* DBGPID0 */
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#define PIDR1_OFFSET 0xFE4 /* DBGPID1 */
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#define PIDR2_OFFSET 0xFE8 /* DBGPID2 */
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#define PIDR3_OFFSET 0xFEC /* DBGPID3 */
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#define PIDR4_OFFSET 0xFD0 /* DBGPID4 */
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#define PIDR5_OFFSET 0xFD4 /* DBGPID5 (Reserved) */
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#define PIDR6_OFFSET 0xFD8 /* DBGPID6 (Reserved) */
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#define PIDR7_OFFSET 0xFDC /* DBGPID7 (Reserved) */
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#define PIDR_REV_MASK 0x0FFF00000ULL /* Revision bits. */
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#define PIDR_PN_MASK 0x000000FFFULL /* Part number bits. */
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#define PIDR_ARM_BITS 0x4000BB000ULL /* These make up the ARM JEP-106 code. */
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enum arm_arch {
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aa_nosupport,
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aa_cortexm,
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aa_cortexa,
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aa_end
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};
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#ifdef PLATFORM_HAS_DEBUG
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#define PIDR_PN_BIT_STRINGS(...) __VA_ARGS__
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#else
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#define PIDR_PN_BIT_STRINGS(...)
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#endif
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/* The part number list was adopted from OpenOCD:
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* https://sourceforge.net/p/openocd/code/ci/406f4/tree/src/target/arm_adi_v5.c#l932
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*
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* The product ID register consists of several parts. For a full description
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* refer to ARM Debug Interface v5 Architecture Specification. Based on the
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* document the pidr is 64 bit long and has the following interpratiation:
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* |7 ID7 reg 0|7 ID6 reg 0|7 ID5 reg 0|7 ID4 reg 0|
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* |0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0| | | | |1|0|0|0|
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* |63 56|55 48|47 40|39 36|35 32|
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* \_______________________ ______________________/\___ __/\___ ___/
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* V V V
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* Reserved, RAZ 4KB |
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* count |
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* JEP-106
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* Continuation Code
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*
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* |7 ID3 reg 0|7 ID2 reg 0|7 ID1 reg 0|7 ID0 reg 0|
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* | | | | | | | | | | | | |1|0|1|1|1|0|1|1| | | | | | | | | | | | |
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* |31 28|27 24|23 20|||18 | 12|11 | 0|
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* \___ __/\__ ___/\___ __/ |\______ _____/\___________ ___________/
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* V V V | V V
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* RevAnd | Revision | JEP-106 Part number
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* | | ID code
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* Customer 19
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* modified `- JEP-106 code is used
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*
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* JEP-106 is a JEDEC standard assigning manufacturer IDs to different
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* manufacturers in case of ARM the full code consisting of the JEP-106
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* Continuation code followed by the code used bit and the JEP-106 code itself
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* results in the code 0x4BB. These are the bits filled in the above bit table.
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*
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* We left out some of the Part numbers included in OpenOCD, we only include
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* the ones that have ARM as the designer.
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*/
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static const struct {
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uint16_t part_number;
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enum arm_arch arch;
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enum cid_class cidc;
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#ifdef PLATFORM_HAS_DEBUG
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const char *type;
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const char *full;
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#endif
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} pidr_pn_bits[] = {
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{0x000, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M3 SCS", "(System Control Space)")},
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{0x001, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ITM", "(Instrumentation Trace Module)")},
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{0x002, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 DWT", "(Data Watchpoint and Trace)")},
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{0x003, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 FBP", "(Flash Patch and Breakpoint)")},
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{0x008, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M0 SCS", "(System Control Space)")},
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{0x00a, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 DWT", "(Data Watchpoint and Trace)")},
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{0x00b, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 BPU", "(Breakpoint Unit)")},
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{0x00c, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M4 SCS", "(System Control Space)")},
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{0x00d, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
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{0x490, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
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{0x4c7, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB", "(Private Peripheral Bus ROM Table)")},
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{0x906, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI", "(Cross Trigger)")},
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{0x907, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB", "(Trace Buffer)")},
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{0x908, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CSTF", "(Trace Funnel)")},
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{0x910, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM9", "(Embedded Trace)")},
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{0x912, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU", "(Trace Port Interface Unit)")},
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{0x913, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
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{0x914, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight SWO", "(Single Wire Output)")},
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{0x917, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight HTM", "(AHB Trace Macrocell)")},
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{0x920, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
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{0x921, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 ETM", "(Embedded Trace)")},
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{0x922, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 CTI", "(Cross Trigger)")},
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{0x923, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 TPIU", "(Trace Port Interface Unit)")},
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{0x924, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ETM", "(Embedded Trace)")},
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{0x925, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ETM", "(Embedded Trace)")},
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{0x930, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 ETM", "(Embedded Trace)")},
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{0x941, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
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{0x950, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")},
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{0x955, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")},
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{0x95f, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PTM", "(Program Trace Macrocell)")},
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{0x961, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TMC", "(Trace Memory Controller)")},
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{0x962, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
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{0x9a0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight PMU", "(Performance Monitoring Unit)")},
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{0x9a1, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
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{0x9a5, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A5 ETM", "(Embedded Trace)")},
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{0x9a7, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 PMU", "(Performance Monitor Unit)")},
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{0x9af, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PMU", "(Performance Monitor Unit)")},
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{0xc05, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A5 Debug", "(Debug Unit)")},
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{0xc07, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A7 Debug", "(Debug Unit)")},
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{0xc08, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A8 Debug", "(Debug Unit)")},
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{0xc09, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A9 Debug", "(Debug Unit)")},
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{0xc0f, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
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{0xc14, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
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{0xfff, aa_end, cidc_unknown, PIDR_PN_BIT_STRINGS("end", "end")}
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};
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extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
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@ -86,18 +251,35 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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addr &= ~3;
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uint64_t pidr = 0;
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uint32_t cidr = 0;
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/* Assemble logical Product ID register value. */
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for (int i = 0; i < 4; i++) {
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uint32_t x = adiv5_mem_read32(ap, addr + 0xfe0 + 4*i);
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uint32_t x = adiv5_mem_read32(ap, addr + PIDR0_OFFSET + 4*i);
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pidr |= (x & 0xff) << (i * 8);
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}
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pidr |= (uint64_t)adiv5_mem_read32(ap, addr + 0xfd0) << 32;
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{
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uint32_t x = adiv5_mem_read32(ap, addr + PIDR4_OFFSET);
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pidr |= (uint64_t)x << 32;
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}
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/* Assemble logical Component ID register value. */
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for (int i = 0; i < 4; i++) {
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uint32_t x = adiv5_mem_read32(ap, addr + 0xff0 + 4*i);
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uint32_t x = adiv5_mem_read32(ap, addr + CIDR0_OFFSET + 4*i);
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cidr |= ((uint64_t)(x & 0xff)) << (i * 8);
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}
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switch (cidr) {
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case CIDR_ROM_TABLE: /* This is a ROM table, probe recursively */
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/* CIDR preamble sanity check */
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if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
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DEBUG("0x%X: 0x%X <- does not match preamble (0x%X)\n", addr, cidr, CID_PREAMBLE);
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return;
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}
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/* Extract Component ID class nibble */
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uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
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DEBUG("0x%X: \"%s\"\n", addr, cidc_debug_strings[cid_class]);
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if (cid_class == cidc_romtab) { /* ROM table, probe recursively */
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for (int i = 0; i < 256; i++) {
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uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
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if (entry == 0)
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@ -108,23 +290,48 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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adiv5_component_probe(ap, addr + (entry & ~0xfff));
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}
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break;
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case CIDR_GENERIC_IP:
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switch (pidr & ~PIDR_REV_MASK) {
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case PIDR_ARMv7MF:
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case PIDR_ARMv7M:
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case PIDR_ARMv6M:
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cortexm_probe(ap);
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break;
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} else {
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/* Check if the component was designed by ARM, we currently do not support,
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* any components by other designers.
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*/
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if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
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DEBUG("0x%X: 0x%llX <- does not match ARM JEP-106\n", addr, pidr);
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return;
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}
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break;
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case CIDR_DEBUG:
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switch (pidr & ~PIDR_REV_MASK) {
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case PIDR_ARMv7A:
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cortexa_probe(ap, addr);
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break;
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/* Extract part number from the part id register. */
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uint16_t part_number = pidr & PIDR_PN_MASK;
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/* Find the part number in our part list and run the appropriate probe
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* routine if applicable.
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*/
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for (int i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
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if (pidr_pn_bits[i].part_number == part_number) {
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DEBUG("0x%X: %s %s\n", addr,
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pidr_pn_bits[i].type,
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pidr_pn_bits[i].full);
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/* Perform sanity check, if we know what to expect as component ID
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* class.
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*/
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if (cid_class != pidr_pn_bits[i].cidc) {
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DEBUG("WARNING: \"%s\" !match expected \"%s\"\n",
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cidc_debug_strings[cid_class],
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cidc_debug_strings[pidr_pn_bits[i].cidc]);
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}
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switch (pidr_pn_bits[i].arch) {
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case aa_cortexm:
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DEBUG("-> cortexm_probe\n");
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cortexm_probe(ap);
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break;
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case aa_cortexa:
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DEBUG("-> cortexa_probe\n");
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cortexa_probe(ap, addr);
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break;
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default:
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DEBUG("-> skip\n");
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}
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break;
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}
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}
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break;
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}
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}
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@ -363,4 +570,3 @@ uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr)
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ret = adiv5_dp_read(ap->dp, addr);
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return ret;
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}
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@ -67,6 +67,8 @@ static struct jtag_dev_descr_s {
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{.idcode = 0x8940303F, .idmask = 0xFFFFFFFF, .descr = "ATMEL: ATMega16."},
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{.idcode = 0x0792603F, .idmask = 0xFFFFFFFF, .descr = "ATMEL: AT91SAM9261."},
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{.idcode = 0x20270013, .idmask = 0xFFFFFFFF, .descr = "Intel: i80386ex."},
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{.idcode = 0x07B7617F, .idmask = 0xFFFFFFFF, .descr = "Broadcom: BCM2835."},
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{.idcode = 0x4BA00477, .idmask = 0xFFFFFFFF, .descr = "Broadcom: BCM2836."},
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{.idcode = 0, .idmask = 0, .descr = "Unknown"},
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};
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