stm32g0: Begun cleaning up the flash write routine
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486fb6504c
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23cf81eb55
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@ -331,6 +331,8 @@ static bool stm32g0_wait_busy(target *const t)
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static void stm32g0_flash_op_finish(target *t)
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{
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target_mem_write32(t, FLASH_SR, FLASH_SR_EOP); // Clear EOP
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/* Clear PG: half-word access not to clear unwanted bits */
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target_mem_write16(t, FLASH_CR, 0);
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stm32g0_flash_lock(t);
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}
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@ -403,12 +405,12 @@ static int stm32g0_flash_erase(target_flash_s *f, target_addr addr, size_t len)
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static int stm32g0_flash_write(target_flash_s *f, target_addr dest, const void *src, size_t len)
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{
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target *const t = f->t;
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int ret = 0;
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stm32g0_priv_s *ps = (stm32g0_priv_s *)t->target_storage;
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if ((dest >= (target_addr)FLASH_OTP_START) && !ps->irreversible_enabled) {
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tc_printf(t, "Irreversible operations disabled\n");
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goto exit_error;
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stm32g0_flash_op_finish(t);
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return -1;
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}
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stm32g0_flash_unlock(t);
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@ -421,28 +423,24 @@ static int stm32g0_flash_write(target_flash_s *f, target_addr dest, const void *
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flash_sr = target_mem_read32(t, FLASH_SR);
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if (target_check_error(t)) {
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DEBUG_WARN("stm32g0 flash write: comm error\n");
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goto exit_error;
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stm32g0_flash_op_finish(t);
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return -1;
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}
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} while (flash_sr & FLASH_SR_BSY_MASK);
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if (flash_sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32g0 flash write error: sr 0x%" PRIx32 "\n", flash_sr);
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goto exit_error;
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stm32g0_flash_op_finish(t);
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return -1;
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}
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if ((dest == (target_addr)FLASH_START) && target_mem_read32(t, FLASH_START) != 0xFFFFFFFF) {
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uint32_t flash_acr = target_mem_read32(t, FLASH_ACR);
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flash_acr &= ~(uint32_t)FLASH_ACR_EMPTY;
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target_mem_write32(t, FLASH_ACR, flash_acr);
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}
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goto exit_cleanup;
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exit_error:
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ret = -1;
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exit_cleanup:
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/* Clear PG: half-word access not to clear unwanted bits */
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target_mem_write16(t, FLASH_CR, (uint16_t)0x0);
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stm32g0_flash_op_finish(t);
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return ret;
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return 0;
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}
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static bool stm32g0_mass_erase(target *t)
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