[stm32h7] add revision command which reads the `DBGMCU_IDC` register
blackmagic PR #476
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@ -35,6 +35,7 @@ static bool stm32h7_cmd_erase_mass(target *t);
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static bool stm32h7_uid(target *t);
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static bool stm32h7_crc(target *t);
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static bool stm32h7_cmd_psize(target *t, int argc, char *argv[]);
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static bool stm32h7_cmd_rev(target *t);
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const struct command_s stm32h7_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32h7_cmd_erase_mass,
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@ -45,6 +46,8 @@ const struct command_s stm32h7_cmd_list[] = {
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"Configure flash write parallelism: (x8|x16|x32|x64(default))"},
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{"uid", (cmd_handler)stm32h7_uid, "Print unique device ID"},
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{"crc", (cmd_handler)stm32h7_crc, "Print CRC of both banks"},
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{"revision", (cmd_handler)stm32h7_cmd_rev,
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"Returns the Device ID and Revision"},
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{NULL, NULL, NULL}
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};
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@ -127,6 +130,7 @@ enum stm32h7_regs
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#define DBGMCU_IDCODE 0x5c001000
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/* Access via 0xe00e1000 does not show device! */
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#define DBGMCU_IDC (DBGMCU_IDCODE + 0)
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#define DBGMCU_CR (DBGMCU_IDCODE + 4)
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#define DBGSLEEP_D1 (1 << 0)
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#define DBGSTOP_D1 (1 << 1)
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@ -515,3 +519,43 @@ static bool stm32h7_cmd_psize(target *t, int argc, char *argv[])
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}
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return true;
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}
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static const struct stm32h7xx_rev {
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uint32_t rev_id;
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char revision;
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} stm32h7xx_revisions[] = {
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{ 0x1000, 'A' },
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{ 0x1001, 'Z' },
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{ 0x1003, 'Y' },
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{ 0x2001, 'X' },
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{ 0x2003, 'V' }
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};
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static bool stm32h7_cmd_rev(target *t)
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{
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/* DBGMCU identity code register */
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uint32_t dbgmcu_idc = target_mem_read32(t, DBGMCU_IDC);
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uint16_t rev_id = (dbgmcu_idc >> 16) & 0xFFFF;
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uint16_t dev_id = dbgmcu_idc & 0xFFF;
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/* Print device */
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switch (dev_id) {
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case 0x450:
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tc_printf(t, "STM32H742/743/753/750\n");
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break;
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default:
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tc_printf(t, "Unknown STM32H7. This driver may not support it!\n");
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}
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/* Print revision */
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char rev = '?';
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for (size_t i = 0;
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i < sizeof(stm32h7xx_revisions)/sizeof(struct stm32h7xx_rev); i++) {
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/* Check for matching revision */
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if (stm32h7xx_revisions[i].rev_id == rev_id) {
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rev = stm32h7xx_revisions[i].revision;
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}
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}
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tc_printf(t, "Revision %c\n", rev);
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return true;
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}
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