Unwind hardfaults in dual-stack mode.
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096e1b32c6
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@ -323,6 +323,14 @@ static const char tdesc_cortex_mf[] =
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" </feature>"
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"</target>";
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#define REG_SP 13
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#define REG_LR 14
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#define REG_PC 15
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#define REG_XPSR 16
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#define REG_MSP 17
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#define REG_PSP 18
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#define REG_SPECIAL 19
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bool
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cortexm_probe(struct target_s *target)
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{
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@ -677,17 +685,29 @@ static int cortexm_fault_unwind(struct target_s *target)
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/* Read registers for post-exception stack pointer */
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target_regs_read(target, regs);
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/* save retcode currently in lr */
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retcode = regs[14];
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retcode = regs[REG_LR];
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bool spsel = retcode & (1<<2);
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bool fpca = !(retcode & (1<<4));
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/* Read stack for pre-exception registers */
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target_mem_read_words(target, stack, regs[13], sizeof(stack));
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regs[14] = stack[5]; /* restore LR to pre-exception state */
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regs[15] = stack[6]; /* restore PC to pre-exception state */
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uint32_t sp = spsel ? regs[REG_PSP] : regs[REG_MSP];
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target_mem_read_words(target, stack, sp, sizeof(stack));
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regs[REG_LR] = stack[5]; /* restore LR to pre-exception state */
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regs[REG_PC] = stack[6]; /* restore PC to pre-exception state */
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/* adjust stack to pop exception state */
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framesize = (retcode & (1<<4)) ? 0x68 : 0x20; /* check for basic vs. extended frame */
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framesize = fpca ? 0x68 : 0x20; /* check for basic vs. extended frame */
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if (stack[7] & (1<<9)) /* check for stack alignment fixup */
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framesize += 4;
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regs[13] += framesize;
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if (spsel) {
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regs[REG_SPECIAL] |= 0x4000000;
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regs[REG_SP] = regs[REG_PSP] += framesize;
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} else {
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regs[REG_SP] = regs[REG_MSP] += framesize;
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}
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if (fpca)
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regs[REG_SPECIAL] |= 0x2000000;
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/* FIXME: stack[7] contains xPSR when this is supported */
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/* although, if we caught the exception it will be unchanged */
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