cortexm: Separate stub loading from running.
This commit is contained in:
parent
9f271d5cd7
commit
31fae032f7
|
@ -616,7 +616,6 @@ static int cortexm_fault_unwind(target *t)
|
||||||
}
|
}
|
||||||
|
|
||||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||||
const uint16_t *stub, uint32_t stublen,
|
|
||||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
|
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
|
||||||
{
|
{
|
||||||
uint32_t regs[t->regs_size / 4];
|
uint32_t regs[t->regs_size / 4];
|
||||||
|
@ -630,7 +629,6 @@ int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||||
regs[16] = 0x1000000;
|
regs[16] = 0x1000000;
|
||||||
regs[19] = 0;
|
regs[19] = 0;
|
||||||
|
|
||||||
target_mem_write(t, loadaddr, stub, stublen);
|
|
||||||
cortexm_regs_write(t, regs);
|
cortexm_regs_write(t, regs);
|
||||||
|
|
||||||
if (target_check_error(t))
|
if (target_check_error(t))
|
||||||
|
|
|
@ -147,7 +147,6 @@ bool cortexm_attach(target *t);
|
||||||
void cortexm_detach(target *t);
|
void cortexm_detach(target *t);
|
||||||
void cortexm_halt_resume(target *t, bool step);
|
void cortexm_halt_resume(target *t, bool step);
|
||||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||||
const uint16_t *stub, uint32_t stublen,
|
|
||||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
||||||
int cortexm_pc_write(target *t, const uint32_t val);
|
int cortexm_pc_write(target *t, const uint32_t val);
|
||||||
|
|
||||||
|
|
|
@ -256,11 +256,11 @@ static int stm32f1_flash_write(target *t, uint32_t dest,
|
||||||
memcpy((uint8_t *)data + offset, src, len);
|
memcpy((uint8_t *)data + offset, src, len);
|
||||||
|
|
||||||
/* Write stub and data to target ram and set PC */
|
/* Write stub and data to target ram and set PC */
|
||||||
target_mem_write(t, STUB_BUFFER_BASE, (void*)data, sizeof(data));
|
target_mem_write(t, SRAM_BASE, stm32f1_flash_write_stub,
|
||||||
return cortexm_run_stub(t, SRAM_BASE, stm32f1_flash_write_stub,
|
sizeof(stm32f1_flash_write_stub));
|
||||||
sizeof(stm32f1_flash_write_stub),
|
target_mem_write(t, STUB_BUFFER_BASE, data, sizeof(data));
|
||||||
dest - offset, STUB_BUFFER_BASE, sizeof(data),
|
return cortexm_run_stub(t, SRAM_BASE, dest - offset,
|
||||||
0);
|
STUB_BUFFER_BASE, sizeof(data), 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool stm32f1_cmd_erase_mass(target *t)
|
static bool stm32f1_cmd_erase_mass(target *t)
|
||||||
|
|
|
@ -216,11 +216,11 @@ static int stm32f4_flash_write(target *t, uint32_t dest,
|
||||||
memcpy((uint8_t *)data + offset, src, len);
|
memcpy((uint8_t *)data + offset, src, len);
|
||||||
|
|
||||||
/* Write buffer to target ram call stub */
|
/* Write buffer to target ram call stub */
|
||||||
|
target_mem_write(t, SRAM_BASE, stm32f4_flash_write_stub,
|
||||||
|
sizeof(stm32f4_flash_write_stub));
|
||||||
target_mem_write(t, STUB_BUFFER_BASE, data, sizeof(data));
|
target_mem_write(t, STUB_BUFFER_BASE, data, sizeof(data));
|
||||||
return cortexm_run_stub(t, SRAM_BASE, stm32f4_flash_write_stub,
|
return cortexm_run_stub(t, SRAM_BASE, dest - offset,
|
||||||
sizeof(stm32f4_flash_write_stub),
|
STUB_BUFFER_BASE, sizeof(data), 0);
|
||||||
dest - offset, STUB_BUFFER_BASE, sizeof(data),
|
|
||||||
0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool stm32f4_cmd_erase_mass(target *t)
|
static bool stm32f4_cmd_erase_mass(target *t)
|
||||||
|
|
Loading…
Reference in New Issue