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target/adiv5: Deassert CDBGRSTREQ after CDBGRSTACK 

In B2.4 of the ADIv5 architecture specification it states that "If
CDBGRSTREQ is removed before the reset controller asserts CDBGRSTACK,
the behavior is UNPREDICTABLE.". Thus we should wait until after
checking for CDBGRSTACK before deasserting CDBGRSTREQ.
This commit is contained in:
James Turton 2022-08-31 23:26:31 +02:00 committed by Rachel Mant
parent 2922539772
commit 32f441dd63
1 changed files with 6 additions and 8 deletions
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14
src/target/adiv5.c
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@ -431,7 +431,7 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
platform_timeout reset_timeout; platform_timeout reset_timeout;
platform_timeout_set(&reset_timeout, cortexm_wait_timeout); platform_timeout_set(&reset_timeout, cortexm_wait_timeout);
platform_nrst_set_val(false); platform_nrst_set_val(false);
while (1) { while (true) {
dhcsr = adiv5_mem_read32(ap, CORTEXM_DHCSR); dhcsr = adiv5_mem_read32(ap, CORTEXM_DHCSR);
if (!(dhcsr & CORTEXM_DHCSR_S_RESET_ST)) if (!(dhcsr & CORTEXM_DHCSR_S_RESET_ST))
break; break;
@ -810,16 +810,12 @@ void adiv5_dp_init(ADIv5_DP_t *dp, const uint32_t idcode)
/* This AP reset logic is described in ADIv5, but fails to work /* This AP reset logic is described in ADIv5, but fails to work
* correctly on STM32. CDBGRSTACK is never asserted, and we * correctly on STM32. CDBGRSTACK is never asserted, and we
* just wait forever. This scenario is described in B2.4.1 * just wait forever. This scenario is described in B2.4.1
* so we have a timeout mechanism in addition to the sensing one. * so we have a timeout mechanism in addition to the sensing one. */
* platform_timeout_set(&timeout, 201);
* Write request for debug reset */ /* Write request for debug reset */
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ); adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
/* Write request for debug reset release */
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
/* Wait for acknowledge */ /* Wait for acknowledge */
while (true) { while (true) {
platform_delay(20);
ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT); ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
if (ctrlstat & ADIV5_DP_CTRLSTAT_CDBGRSTACK) { if (ctrlstat & ADIV5_DP_CTRLSTAT_CDBGRSTACK) {
DEBUG_INFO("RESET_SEQ succeeded.\n"); DEBUG_INFO("RESET_SEQ succeeded.\n");
@ -830,6 +826,8 @@ void adiv5_dp_init(ADIv5_DP_t *dp, const uint32_t idcode)
break; break;
} }
} }
/* Write request for debug reset release */
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
/* Probe for APs on this DP */ /* Probe for APs on this DP */
size_t invalid_aps = 0; size_t invalid_aps = 0;