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lpc: split out common code and rewrite to use new interface.

This commit is contained in:
Gareth McMullin 2015-04-04 19:15:03 -07:00
parent cd5d569d38
commit 3d8b34f180
5 changed files with 255 additions and 555 deletions
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1
src/Makefile
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@ -28,6 +28,7 @@ SRC = \
jtag_scan.c \ jtag_scan.c \
jtagtap.c \ jtagtap.c \
lmi.c \ lmi.c \
lpc_common.c \
lpc11xx.c \ lpc11xx.c \
lpc43xx.c \ lpc43xx.c \
kinetis.c \ kinetis.c \

91
src/include/lpc_common.h
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@ -20,64 +20,49 @@
#ifndef __LPC_COMMON_H #ifndef __LPC_COMMON_H
#define __LPC_COMMON_H #define __LPC_COMMON_H
#define IAP_CMD_INIT 49 enum iap_cmd {
#define IAP_CMD_PREPARE 50 IAP_CMD_INIT = 49,
#define IAP_CMD_PROGRAM 51 IAP_CMD_PREPARE = 50,
#define IAP_CMD_ERASE 52 IAP_CMD_PROGRAM = 51,
#define IAP_CMD_BLANKCHECK 53 IAP_CMD_ERASE = 52,
#define IAP_CMD_SET_ACTIVE_BANK 60 IAP_CMD_BLANKCHECK = 53,
IAP_CMD_SET_ACTIVE_BANK = 60,
};
#define IAP_STATUS_CMD_SUCCESS 0 enum iap_status {
#define IAP_STATUS_INVALID_COMMAND 1 IAP_STATUS_CMD_SUCCESS = 0,
#define IAP_STATUS_SRC_ADDR_ERROR 2 IAP_STATUS_INVALID_COMMAND = 1,
#define IAP_STATUS_DST_ADDR_ERROR 3 IAP_STATUS_SRC_ADDR_ERROR = 2,
#define IAP_STATUS_SRC_ADDR_NOT_MAPPED 4 IAP_STATUS_DST_ADDR_ERROR = 3,
#define IAP_STATUS_DST_ADDR_NOT_MAPPED 5 IAP_STATUS_SRC_ADDR_NOT_MAPPED = 4,
#define IAP_STATUS_COUNT_ERROR 6 IAP_STATUS_DST_ADDR_NOT_MAPPED = 5,
#define IAP_STATUS_INVALID_SECTOR 7 IAP_STATUS_COUNT_ERROR = 6,
#define IAP_STATUS_SECTOR_NOT_BLANK 8 IAP_STATUS_INVALID_SECTOR = 7,
#define IAP_STATUS_SECTOR_NOT_PREPARED 9 IAP_STATUS_SECTOR_NOT_BLANK = 8,
#define IAP_STATUS_COMPARE_ERROR 10 IAP_STATUS_SECTOR_NOT_PREPARED = 9,
#define IAP_STATUS_BUSY 11 IAP_STATUS_COMPARE_ERROR = 10,
IAP_STATUS_BUSY = 11,
};
/* CPU Frequency */ /* CPU Frequency */
#define CPU_CLK_KHZ 12000 #define CPU_CLK_KHZ 12000
struct flash_param { struct lpc_flash {
uint16_t opcode;/* opcode to return to after calling the ROM */ struct target_flash f;
uint16_t pad0; uint8_t base_sector;
uint32_t command;/* IAP command */ uint8_t bank;
union { /* Info filled in by specific driver */
uint32_t words[5];/* command parameters */ void (*wdt_kick)(target *t);
struct { uint32_t iap_entry;
uint32_t start_sector; uint32_t iap_ram;
uint32_t end_sector; uint32_t iap_msp;
uint32_t flash_bank; };
} prepare;
struct { struct lpc_flash *lpc_add_flash(target *t, uint32_t addr, size_t length);
uint32_t start_sector; enum iap_status lpc_iap_call(struct lpc_flash *f, enum iap_cmd cmd, ...);
uint32_t end_sector; int lpc_flash_erase(struct target_flash *f, uint32_t addr, size_t len);
uint32_t cpu_clk_khz; int lpc_flash_write(struct target_flash *f,
uint32_t flash_bank; uint32_t dest, const void *src, size_t len);
} erase;
struct {
uint32_t dest;
uint32_t source;
uint32_t byte_count;
uint32_t cpu_clk_khz;
} program;
struct {
uint32_t start_sector;
uint32_t end_sector;
uint32_t flash_bank;
} blank_check;
struct {
uint32_t flash_bank;
uint32_t cpu_clk_khz;
} make_active;
};
uint32_t result[5]; /* result data */
} __attribute__((aligned(4)));
#endif #endif

240
src/lpc11xx.c
View File

@ -23,63 +23,27 @@
#include "cortexm.h" #include "cortexm.h"
#include "lpc_common.h" #include "lpc_common.h"
#define IAP_PGM_CHUNKSIZE 256 /* should fit in RAM on any device */ #define IAP_PGM_CHUNKSIZE 512 /* should fit in RAM on any device */
#define MIN_RAM_SIZE 1024
#define MIN_RAM_SIZE_FOR_LPC8xx 1024
#define MIN_RAM_SIZE_FOR_LPC1xxx 2048
#define RAM_USAGE_FOR_IAP_ROUTINES 32 /* IAP routines use 32 bytes at top of ram */ #define RAM_USAGE_FOR_IAP_ROUTINES 32 /* IAP routines use 32 bytes at top of ram */
#define IAP_ENTRYPOINT 0x1fff1ff1 #define IAP_ENTRYPOINT 0x1fff1ff1
#define IAP_RAM_BASE 0x10000000 #define IAP_RAM_BASE 0x10000000
static const char lpc8xx_driver[] = "lpc8xx"; static int lpc11xx_flash_write(struct target_flash *f,
static const char lpc11xx_driver[] = "lpc11xx"; uint32_t dest, const void *src, size_t len);
static void lpc11x_iap_call(target *t, struct flash_param *param, unsigned param_len);
static int lpc11xx_flash_prepare(target *t, uint32_t addr, int len);
static int lpc11xx_flash_erase(target *t, uint32_t addr, size_t len);
static int lpc11xx_flash_write(target *t, uint32_t dest, const uint8_t *src,
size_t len);
struct flash_program { void lpc11xx_add_flash(target *t, uint32_t addr, size_t len, size_t erasesize)
struct flash_param p; {
uint8_t data[IAP_PGM_CHUNKSIZE]; struct lpc_flash *lf = lpc_add_flash(t, addr, len);
}; lf->f.blocksize = erasesize;
lf->f.buf_size = IAP_PGM_CHUNKSIZE;
/* lf->f.write_buf = lpc11xx_flash_write;
* Note that this memory map is actually for the largest of the lpc11xx devices; lf->iap_entry = IAP_ENTRYPOINT;
* There seems to be no good way to decode the part number to determine the RAM lf->iap_ram = IAP_RAM_BASE;
* and flash sizes. lf->iap_msp = IAP_RAM_BASE + MIN_RAM_SIZE - RAM_USAGE_FOR_IAP_ROUTINES;
*/ }
static const char lpc11xx_xml_memory_map[] = "<?xml version=\"1.0\"?>"
/* "<!DOCTYPE memory-map "
" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
"<memory-map>"
" <memory type=\"flash\" start=\"0x00000000\" length=\"0x20000\">"
" <property name=\"blocksize\">0x1000</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x2000\"/>"
"</memory-map>";
/*
* Memory map for the lpc8xx devices, which otherwise look much like the lpc11xx.
*
* We could decode the RAM/flash sizes, but we just encode the largest possible here.
*
* Note that the LPC810 and LPC811 map their flash oddly; see the NXP LPC800 user
* manual (UM10601) for more details.
*/
static const char lpc8xx_xml_memory_map[] = "<?xml version=\"1.0\"?>"
/* "<!DOCTYPE memory-map "
" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
"<memory-map>"
" <memory type=\"flash\" start=\"0x00000000\" length=\"0x4000\">"
" <property name=\"blocksize\">0x400</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x1000\"/>"
"</memory-map>";
bool bool
lpc11xx_probe(target *t) lpc11xx_probe(target *t)
@ -122,183 +86,33 @@ lpc11xx_probe(target *t)
case 0x2972402B: /* lpc11u23/301 */ case 0x2972402B: /* lpc11u23/301 */
case 0x2988402B: /* lpc11u24x/301 */ case 0x2988402B: /* lpc11u24x/301 */
case 0x2980002B: /* lpc11u24x/401 */ case 0x2980002B: /* lpc11u24x/401 */
t->driver = lpc11xx_driver; t->driver = "LPC11xx";
t->xml_mem_map = lpc11xx_xml_memory_map; target_add_ram(t, 0x10000000, 0x2000);
t->flash_erase = lpc11xx_flash_erase; lpc11xx_add_flash(t, 0x00000000, 0x20000, 0x1000);
t->flash_write = lpc11xx_flash_write;
return true; return true;
case 0x1812202b: /* LPC812M101FDH20 */ case 0x1812202b: /* LPC812M101FDH20 */
t->driver = lpc8xx_driver; t->driver = "LPC8xx";
t->xml_mem_map = lpc8xx_xml_memory_map; target_add_ram(t, 0x10000000, 0x1000);
t->flash_erase = lpc11xx_flash_erase; lpc11xx_add_flash(t, 0x00000000, 0x4000, 0x400);
t->flash_write = lpc11xx_flash_write;
return true; return true;
} }
return false; return false;
} }
static void static int lpc11xx_flash_write(struct target_flash *f,
lpc11x_iap_call(target *t, struct flash_param *param, unsigned param_len) uint32_t dest, const void *src, size_t len)
{ {
uint32_t regs[t->regs_size / sizeof(uint32_t)]; if (dest == 0) {
/* Fill in the magic vector to allow booting the flash */
/* fill out the remainder of the parameters and copy the structure to RAM */ uint32_t *w = (uint32_t *)src;
param->opcode = ARM_THUMB_BREAKPOINT;
param->pad0 = 0x0000;
target_mem_write(t, IAP_RAM_BASE, param, param_len);
/* set up for the call to the IAP ROM */
target_regs_read(t, regs);
regs[0] = IAP_RAM_BASE + offsetof(struct flash_param, command);
regs[1] = IAP_RAM_BASE + offsetof(struct flash_param, result);
// stack pointer - top of the smallest ram less 32 for IAP usage
if (t->driver == lpc8xx_driver)
regs[REG_MSP] = IAP_RAM_BASE + MIN_RAM_SIZE_FOR_LPC8xx - RAM_USAGE_FOR_IAP_ROUTINES;
else
regs[REG_MSP] = IAP_RAM_BASE + MIN_RAM_SIZE_FOR_LPC1xxx - RAM_USAGE_FOR_IAP_ROUTINES;
regs[REG_LR] = IAP_RAM_BASE | 1;
regs[REG_PC] = IAP_ENTRYPOINT;
target_regs_write(t, regs);
/* start the target and wait for it to halt again */
target_halt_resume(t, 0);
while (!target_halt_wait(t));
/* copy back just the parameters structure */
target_mem_read(t, param, IAP_RAM_BASE, sizeof(struct flash_param));
}
static int flash_page_size(target *t)
{
if (t->driver == lpc8xx_driver)
return 1024;
else
return 4096;
}
static int
lpc11xx_flash_prepare(target *t, uint32_t addr, int len)
{
struct flash_program flash_pgm;
/* prepare the sector(s) to be erased */
memset(&flash_pgm.p, 0, sizeof(flash_pgm.p));
flash_pgm.p.command = IAP_CMD_PREPARE;
flash_pgm.p.prepare.start_sector = addr / flash_page_size(t);
flash_pgm.p.prepare.end_sector = (addr + len - 1) / flash_page_size(t);
lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
return 0;
}
static int
lpc11xx_flash_erase(target *t, uint32_t addr, size_t len)
{
struct flash_program flash_pgm;
if (addr % flash_page_size(t))
return -1;
/* prepare... */
if (lpc11xx_flash_prepare(t, addr, len))
return -1;
/* and now erase them */
flash_pgm.p.command = IAP_CMD_ERASE;
flash_pgm.p.erase.start_sector = addr / flash_page_size(t);
flash_pgm.p.erase.end_sector = (addr + len - 1) / flash_page_size(t);
flash_pgm.p.erase.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
/* check erase ok */
flash_pgm.p.command = IAP_CMD_BLANKCHECK;
lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
return 0;
}
static int
lpc11xx_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len)
{
unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE;
unsigned last_chunk = (dest + len - 1) / IAP_PGM_CHUNKSIZE;
unsigned chunk_offset = dest % IAP_PGM_CHUNKSIZE;
unsigned chunk;
struct flash_program flash_pgm;
for (chunk = first_chunk; chunk <= last_chunk; chunk++) {
DEBUG("chunk %u len %zu\n", chunk, len);
/* first and last chunk may require special handling */
if ((chunk == first_chunk) || (chunk == last_chunk)) {
/* fill with all ff to avoid sector rewrite corrupting other writes */
memset(flash_pgm.data, 0xff, sizeof(flash_pgm.data));
/* copy as much as fits */
size_t copylen = IAP_PGM_CHUNKSIZE - chunk_offset;
if (copylen > len)
copylen = len;
memcpy(flash_pgm.data + chunk_offset, src, copylen);
/* if we are programming the vectors, calculate the magic number */
if ((chunk == 0) && (chunk_offset == 0)) {
if (copylen < 32) {
/* we have to be programming at least the first 8 vectors... */
return -1;
}
uint32_t *w = (uint32_t *)(&flash_pgm.data[0]);
uint32_t sum = 0; uint32_t sum = 0;
for (unsigned i = 0; i < 7; i++) for (unsigned i = 0; i < 7; i++)
sum += w[i]; sum += w[i];
w[7] = ~sum + 1; w[7] = ~sum + 1;
} }
return lpc_flash_write(f, dest, src, len);
/* update to suit */
len -= copylen;
src += copylen;
chunk_offset = 0;
} else {
/* interior chunk, must be aligned and full-sized */
memcpy(flash_pgm.data, src, IAP_PGM_CHUNKSIZE);
len -= IAP_PGM_CHUNKSIZE;
src += IAP_PGM_CHUNKSIZE;
}
/* prepare... */
if (lpc11xx_flash_prepare(t, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE))
return -1;
/* set the destination address and program */
flash_pgm.p.command = IAP_CMD_PROGRAM;
flash_pgm.p.program.dest = chunk * IAP_PGM_CHUNKSIZE;
flash_pgm.p.program.source = IAP_RAM_BASE + offsetof(struct flash_program, data);
flash_pgm.p.program.byte_count = IAP_PGM_CHUNKSIZE;
flash_pgm.p.program.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
}
return 0;
} }

337
src/lpc43xx.c
View File

@ -44,31 +44,14 @@
#define IAP_PGM_CHUNKSIZE 4096 #define IAP_PGM_CHUNKSIZE 4096
#define FLASH_BANK_A_BASE 0x1A000000
#define FLASH_BANK_A_SIZE 0x80000
#define FLASH_BANK_B_BASE 0x1B000000
#define FLASH_BANK_B_SIZE 0x80000
#define FLASH_NUM_BANK 2 #define FLASH_NUM_BANK 2
#define FLASH_NUM_SECTOR 15 #define FLASH_NUM_SECTOR 15
#define FLASH_LARGE_SECTOR_OFFSET 0x00010000
struct flash_program {
struct flash_param p;
uint8_t data[IAP_PGM_CHUNKSIZE];
};
static bool lpc43xx_cmd_erase(target *t, int argc, const char *argv[]); static bool lpc43xx_cmd_erase(target *t, int argc, const char *argv[]);
static bool lpc43xx_cmd_reset(target *t, int argc, const char *argv[]); static bool lpc43xx_cmd_reset(target *t, int argc, const char *argv[]);
static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[]); static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[]);
static int lpc43xx_flash_init(target *t); static int lpc43xx_flash_init(target *t);
static void lpc43xx_iap_call(target *t, struct flash_param *param, static int lpc43xx_flash_erase(struct target_flash *f, uint32_t addr, size_t len);
unsigned param_len);
static int lpc43xx_flash_prepare(target *t,
uint32_t addr, int len);
static int lpc43xx_flash_erase(target *t, uint32_t addr, size_t len);
static int lpc43xx_flash_write(target *t,
uint32_t dest, const uint8_t *src, size_t len);
static void lpc43xx_set_internal_clock(target *t); static void lpc43xx_set_internal_clock(target *t);
static void lpc43xx_wdt_set_period(target *t); static void lpc43xx_wdt_set_period(target *t);
static void lpc43xx_wdt_pet(target *t); static void lpc43xx_wdt_pet(target *t);
@ -80,34 +63,26 @@ const struct command_s lpc43xx_cmd_list[] = {
{NULL, NULL, NULL} {NULL, NULL, NULL}
}; };
/* blocksize is the erasure block size */ void lpc43xx_add_flash(target *t, uint32_t iap_entry,
static const char lpc4337_xml_memory_map[] = "<?xml version=\"1.0\"?>" uint8_t bank, uint8_t base_sector,
/* uint32_t addr, size_t len, size_t erasesize)
"<!DOCTYPE memory-map " {
" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\"" struct lpc_flash *lf = lpc_add_flash(t, addr, len);
"\"http://sourceware.org/gdb/gdb-memory-map.dtd\">" lf->f.erase = lpc43xx_flash_erase;
*/ lf->f.blocksize = erasesize;
"<memory-map>" lf->f.buf_size = IAP_PGM_CHUNKSIZE;
" <memory type=\"ram\" start=\"0x0\" length=\"0x1A000000\"/>" lf->bank = bank;
" <memory type=\"flash\" start=\"0x1A000000\" length=\"0x10000\">" lf->base_sector = base_sector;
" <property name=\"blocksize\">0x2000</property>" lf->iap_entry = iap_entry;
" </memory>" lf->iap_ram = IAP_RAM_BASE;
" <memory type=\"flash\" start=\"0x1A010000\" length=\"0x70000\">" lf->iap_msp = IAP_RAM_BASE + IAP_RAM_SIZE;
" <property name=\"blocksize\">0x10000</property>" lf->wdt_kick = lpc43xx_wdt_pet;
" </memory>" }
" <memory type=\"ram\" start=\"0x1A080000\" length=\"0x00F80000\"/>"
" <memory type=\"flash\" start=\"0x1B000000\" length=\"0x10000\">"
" <property name=\"blocksize\">0x2000</property>"
" </memory>"
" <memory type=\"flash\" start=\"0x1B010000\" length=\"0x70000\">"
" <property name=\"blocksize\">0x10000</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x1B080000\" length=\"0xE4F80000\"/>"
"</memory-map>";
bool lpc43xx_probe(target *t) bool lpc43xx_probe(target *t)
{ {
uint32_t chipid, cpuid; uint32_t chipid, cpuid;
uint32_t iap_entry;
chipid = target_mem_read32(t, LPC43XX_CHIPID); chipid = target_mem_read32(t, LPC43XX_CHIPID);
cpuid = target_mem_read32(t, ARM_CPUID); cpuid = target_mem_read32(t, ARM_CPUID);
@ -120,10 +95,20 @@ bool lpc43xx_probe(target *t)
if (cpuid == 0x410FC241) if (cpuid == 0x410FC241)
{ {
/* LPC4337 */ /* LPC4337 */
t->xml_mem_map = lpc4337_xml_memory_map; iap_entry = target_mem_read32(t,
t->flash_erase = lpc43xx_flash_erase; IAP_ENTRYPOINT_LOCATION);
t->flash_write = lpc43xx_flash_write; target_add_ram(t, 0, 0x1A000000);
lpc43xx_add_flash(t, iap_entry, 0, 0,
0x1A000000, 0x10000, 0x2000);
lpc43xx_add_flash(t, iap_entry, 0, 8,
0x1A010000, 0x70000, 0x10000);
target_add_ram(t, 0x1A080000, 0xF80000);
lpc43xx_add_flash(t, iap_entry, 1, 0,
0x1B000000, 0x10000, 0x2000);
lpc43xx_add_flash(t, iap_entry, 1, 8,
0x1B010000, 0x70000, 0x10000);
target_add_commands(t, lpc43xx_cmd_list, "LPC43xx"); target_add_commands(t, lpc43xx_cmd_list, "LPC43xx");
target_add_ram(t, 0x1B080000, 0xE4F80000UL);
} }
break; break;
case 0x4100C200: case 0x4100C200:
@ -173,35 +158,19 @@ static bool lpc43xx_cmd_erase(target *t, int argc, const char *argv[])
(void)argc; (void)argc;
(void)argv; (void)argv;
uint32_t bank = 0;
struct flash_program flash_pgm;
lpc43xx_flash_init(t); lpc43xx_flash_init(t);
for (bank = 0; bank < FLASH_NUM_BANK; bank++) for (int bank = 0; bank < FLASH_NUM_BANK; bank++)
{ {
flash_pgm.p.command = IAP_CMD_PREPARE; struct lpc_flash *f = (struct lpc_flash *)t->flash;
flash_pgm.p.prepare.start_sector = 0; if (lpc_iap_call(f, IAP_CMD_PREPARE,
flash_pgm.p.prepare.end_sector = FLASH_NUM_SECTOR-1; 0, FLASH_NUM_SECTOR-1, bank))
flash_pgm.p.prepare.flash_bank = bank;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return false; return false;
}
flash_pgm.p.command = IAP_CMD_ERASE; if (lpc_iap_call(f, IAP_CMD_ERASE,
flash_pgm.p.erase.start_sector = 0; 0, FLASH_NUM_SECTOR-1, CPU_CLK_KHZ, bank))
flash_pgm.p.prepare.end_sector = FLASH_NUM_SECTOR-1;
flash_pgm.p.erase.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.erase.flash_bank = bank;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS)
{
return false; return false;
} }
}
gdb_outf("Erase OK.\n"); gdb_outf("Erase OK.\n");
@ -216,215 +185,26 @@ static int lpc43xx_flash_init(target *t)
/* Force internal clock */ /* Force internal clock */
lpc43xx_set_internal_clock(t); lpc43xx_set_internal_clock(t);
struct flash_program flash_pgm;
/* Initialize flash IAP */ /* Initialize flash IAP */
flash_pgm.p.command = IAP_CMD_INIT; struct lpc_flash *f = (struct lpc_flash *)t->flash;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; if (lpc_iap_call(f, IAP_CMD_INIT))
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS)
return -1; return -1;
return 0; return 0;
} }
static int lpc43xx_flash_erase(struct target_flash *f, uint32_t addr, size_t len)
/**
* @brief find a sector number given linear offset
*/
static int32_t flash_bank(uint32_t addr)
{ {
if ((addr >= FLASH_BANK_A_BASE) && if (lpc43xx_flash_init(f->t))
(addr < (FLASH_BANK_A_BASE + FLASH_BANK_A_SIZE)))
return 0;
if ((addr >= FLASH_BANK_B_BASE) &&
(addr < (FLASH_BANK_B_BASE + FLASH_BANK_B_SIZE)))
return 1;
return -1;
}
/**
* @brief find a sector number given linear offset
*/
static int32_t sector_number(uint32_t addr)
{
int32_t bank = flash_bank(addr);
switch (bank) {
case 0:
addr = addr - FLASH_BANK_A_BASE;
break;
case 1:
addr = addr - FLASH_BANK_B_BASE;
break;
default:
return -1;
}
/* from 47.5 "Sector numbers" (page 1218) UM10503.pdf (Rev 1.6) */
if (addr < FLASH_LARGE_SECTOR_OFFSET) {
return addr >> 13;
} else {
return 8 + ((addr - FLASH_LARGE_SECTOR_OFFSET) >> 16);
}
}
static void lpc43xx_iap_call(target *t, struct flash_param *param, unsigned param_len)
{
uint32_t regs[t->regs_size / sizeof(uint32_t)];
uint32_t iap_entry;
/* Pet WDT before each IAP call, if it is on */
lpc43xx_wdt_pet(t);
target_mem_read(t, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry));
/* fill out the remainder of the parameters and copy the structure to RAM */
param->opcode = ARM_THUMB_BREAKPOINT;
param->pad0 = 0x0000;
target_mem_write(t, IAP_RAM_BASE, param, param_len);
/* set up for the call to the IAP ROM */
target_regs_read(t, regs);
regs[0] = IAP_RAM_BASE + offsetof(struct flash_param, command);
regs[1] = IAP_RAM_BASE + offsetof(struct flash_param, result);
regs[REG_MSP] = IAP_RAM_BASE + IAP_RAM_SIZE;
regs[REG_LR] = IAP_RAM_BASE | 1;
regs[REG_PC] = iap_entry;
target_regs_write(t, regs);
/* start the target and wait for it to halt again */
target_halt_resume(t, 0);
while (!target_halt_wait(t));
/* copy back just the parameters structure */
target_mem_read(t, param, IAP_RAM_BASE, sizeof(struct flash_param));
}
static int lpc43xx_flash_prepare(target *t, uint32_t addr, int len)
{
struct flash_program flash_pgm;
/* prepare the sector(s) to be erased */
memset(&flash_pgm.p, 0, sizeof(flash_pgm.p));
flash_pgm.p.command = IAP_CMD_PREPARE;
flash_pgm.p.prepare.start_sector = sector_number(addr);
flash_pgm.p.prepare.end_sector = sector_number(addr+len);
flash_pgm.p.prepare.flash_bank = flash_bank(addr);
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
return 0;
}
static int lpc43xx_flash_erase(target *t, uint32_t addr, size_t len)
{
struct flash_program flash_pgm;
/* min block size */
if (addr % 8192)
return -1; return -1;
/* init */ return lpc_flash_erase(f, addr, len);
if (lpc43xx_flash_init(t))
return -1;
/* prepare... */
if (lpc43xx_flash_prepare(t, addr, len))
return -1;
/* and now erase them */
flash_pgm.p.command = IAP_CMD_ERASE;
flash_pgm.p.erase.start_sector = sector_number(addr);
flash_pgm.p.erase.end_sector = sector_number(addr+len);
flash_pgm.p.erase.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.erase.flash_bank = flash_bank(addr);
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
/* check erase ok */
flash_pgm.p.command = IAP_CMD_BLANKCHECK;
flash_pgm.p.blank_check.start_sector = sector_number(addr);
flash_pgm.p.blank_check.end_sector = sector_number(addr+len);
flash_pgm.p.blank_check.flash_bank = flash_bank(addr);
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
return 0;
} }
static void lpc43xx_set_internal_clock(target *t) static void lpc43xx_set_internal_clock(target *t)
{ {
const uint32_t val2 = (1 << 11) | (1 << 24); const uint32_t val2 = (1 << 11) | (1 << 24);
target_mem_write(t, 0x40050000 + 0x06C, &val2, sizeof(val2)); target_mem_write32(t, 0x40050000 + 0x06C, val2);
}
static int lpc43xx_flash_write(target *t,
uint32_t dest, const uint8_t *src, size_t len)
{
unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE;
unsigned last_chunk = (dest + len - 1) / IAP_PGM_CHUNKSIZE;
unsigned chunk_offset = dest % IAP_PGM_CHUNKSIZE;
unsigned chunk;
struct flash_program flash_pgm;
for (chunk = first_chunk; chunk <= last_chunk; chunk++) {
DEBUG("chunk %u len %zu\n", chunk, len);
/* first and last chunk may require special handling */
if ((chunk == first_chunk) || (chunk == last_chunk)) {
/* fill with all ff to avoid sector rewrite corrupting other writes */
memset(flash_pgm.data, 0xff, sizeof(flash_pgm.data));
/* copy as much as fits */
size_t copylen = IAP_PGM_CHUNKSIZE - chunk_offset;
if (copylen > len)
copylen = len;
memcpy(flash_pgm.data + chunk_offset, src, copylen);
/* update to suit */
len -= copylen;
src += copylen;
chunk_offset = 0;
} else {
/* interior chunk, must be aligned and full-sized */
memcpy(flash_pgm.data, src, IAP_PGM_CHUNKSIZE);
len -= IAP_PGM_CHUNKSIZE;
src += IAP_PGM_CHUNKSIZE;
}
/* prepare... */
if (lpc43xx_flash_prepare(t, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE))
return -1;
/* set the destination address and program */
flash_pgm.p.command = IAP_CMD_PROGRAM;
flash_pgm.p.program.dest = chunk * IAP_PGM_CHUNKSIZE;
flash_pgm.p.program.source = IAP_RAM_BASE + offsetof(struct flash_program, data);
flash_pgm.p.program.byte_count = IAP_PGM_CHUNKSIZE;
flash_pgm.p.program.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
return -1;
}
}
return 0;
} }
/* /*
@ -450,15 +230,10 @@ static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[])
} }
lpc43xx_flash_init(t); lpc43xx_flash_init(t);
struct flash_program flash_pgm;
/* special command to compute/write magic vector for signature */ /* special command to compute/write magic vector for signature */
flash_pgm.p.command = IAP_CMD_SET_ACTIVE_BANK; struct lpc_flash *f = (struct lpc_flash *)t->flash;
flash_pgm.p.make_active.flash_bank = bank; if (lpc_iap_call(f, IAP_CMD_SET_ACTIVE_BANK, bank, CPU_CLK_KHZ)) {
flash_pgm.p.make_active.cpu_clk_khz = CPU_CLK_KHZ;
flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS;
lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm));
if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) {
gdb_outf("Set bootable failed.\n"); gdb_outf("Set bootable failed.\n");
return false; return false;
} }
@ -469,33 +244,23 @@ static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[])
static void lpc43xx_wdt_set_period(target *t) static void lpc43xx_wdt_set_period(target *t)
{ {
uint32_t wdt_mode = 0;
/* Check if WDT is on */ /* Check if WDT is on */
target_mem_read(t, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); uint32_t wdt_mode = target_mem_read32(t, LPC43XX_WDT_MODE);
/* If WDT on, we can't disable it, but we may be able to set a long period */ /* If WDT on, we can't disable it, but we may be able to set a long period */
if (wdt_mode && !(wdt_mode & LPC43XX_WDT_PROTECT)) if (wdt_mode && !(wdt_mode & LPC43XX_WDT_PROTECT))
{ target_mem_write32(t, LPC43XX_WDT_CNT, LPC43XX_WDT_PERIOD_MAX);
const uint32_t wdt_period = LPC43XX_WDT_PERIOD_MAX;
target_mem_write(t, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period));
}
} }
static void lpc43xx_wdt_pet(target *t) static void lpc43xx_wdt_pet(target *t)
{ {
uint32_t wdt_mode = 0;
/* Check if WDT is on */ /* Check if WDT is on */
target_mem_read(t, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); uint32_t wdt_mode = target_mem_read32(t, LPC43XX_WDT_MODE);
/* If WDT on, pet */ /* If WDT on, pet */
if (wdt_mode) if (wdt_mode) {
{ target_mem_write32(t, LPC43XX_WDT_FEED, 0xAA);
const uint32_t feed1 = 0xAA;; target_mem_write32(t, LPC43XX_WDT_FEED, 0xFF);
const uint32_t feed2 = 0x55;;
target_mem_write(t, LPC43XX_WDT_FEED, &feed1, sizeof(feed1));
target_mem_write(t, LPC43XX_WDT_FEED, &feed2, sizeof(feed2));
} }
} }

135
src/lpc_common.c Normal file
View File

@ -0,0 +1,135 @@
/*
* This file is part of the Black Magic Debug project.
*
* Copyright (C) 2015 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "general.h"
#include "target.h"
#include "cortexm.h"
#include "lpc_common.h"
#include <stdarg.h>
struct flash_param {
uint16_t opcode;
uint16_t pad0;
uint32_t command;
uint32_t words[4];
uint32_t result;
} __attribute__((aligned(4)));
struct lpc_flash *lpc_add_flash(target *t, uint32_t addr, size_t length)
{
struct lpc_flash *lf = calloc(1, sizeof(*lf));
struct target_flash *f = &lf->f;
f->start = addr;
f->length = length;
f->erase = lpc_flash_erase;
f->write = target_flash_write_buffered;
f->done = target_flash_done_buffered;
f->write_buf = lpc_flash_write;
f->erased = 0xff;
target_add_flash(t, f);
return lf;
}
enum iap_status lpc_iap_call(struct lpc_flash *f, enum iap_cmd cmd, ...)
{
target *t = f->f.t;
struct flash_param param = {
.opcode = ARM_THUMB_BREAKPOINT,
.command = cmd,
};
/* Pet WDT before each IAP call, if it is on */
if (f->wdt_kick)
f->wdt_kick(t);
/* fill out the remainder of the parameters */
va_list ap;
va_start(ap, cmd);
for (int i = 0; i < 4; i++)
param.words[i] = va_arg(ap, uint32_t);
va_end(ap);
/* copy the structure to RAM */
target_mem_write(t, f->iap_ram, &param, sizeof(param));
/* set up for the call to the IAP ROM */
uint32_t regs[t->regs_size / sizeof(uint32_t)];
target_regs_read(t, regs);
regs[0] = f->iap_ram + offsetof(struct flash_param, command);
regs[1] = f->iap_ram + offsetof(struct flash_param, result);
regs[REG_MSP] = f->iap_msp;
regs[REG_LR] = f->iap_ram | 1;
regs[REG_PC] = f->iap_entry;
target_regs_write(t, regs);
/* start the target and wait for it to halt again */
target_halt_resume(t, false);
while (!target_halt_wait(t));
/* copy back just the parameters structure */
target_mem_read(t, &param, f->iap_ram, sizeof(param));
return param.result;
}
static uint8_t lpc_sector_for_addr(struct lpc_flash *f, uint32_t addr)
{
return f->base_sector + (addr - f->f.start) / f->f.blocksize;
}
int lpc_flash_erase(struct target_flash *tf, uint32_t addr, size_t len)
{
struct lpc_flash *f = (struct lpc_flash *)tf;
uint32_t start = lpc_sector_for_addr(f, addr);
uint32_t end = lpc_sector_for_addr(f, addr + len - 1);
if (lpc_iap_call(f, IAP_CMD_PREPARE, start, end, f->bank))
return -1;
/* and now erase them */
if (lpc_iap_call(f, IAP_CMD_ERASE, start, end, CPU_CLK_KHZ, f->bank))
return -2;
/* check erase ok */
if (lpc_iap_call(f, IAP_CMD_BLANKCHECK, start, end, f->bank))
return -3;
return 0;
}
int lpc_flash_write(struct target_flash *tf,
uint32_t dest, const void *src, size_t len)
{
struct lpc_flash *f = (struct lpc_flash *)tf;
/* prepare... */
uint32_t sector = lpc_sector_for_addr(f, dest);
if (lpc_iap_call(f, IAP_CMD_PREPARE, sector, sector, f->bank))
return -1;
/* Write payload to target ram */
uint32_t bufaddr = ALIGN(f->iap_ram + sizeof(struct flash_param), 4);
target_mem_write(f->f.t, bufaddr, src, len);
/* set the destination address and program */
if (lpc_iap_call(f, IAP_CMD_PROGRAM, dest, bufaddr, len, CPU_CLK_KHZ))
return -2;
return 0;
}