Revert "STM32F4: Add handling of second bank and dual boot devices."
This reverts commit 536482f804.
This commit is contained in:
Gareth McMullin
parent
09fbe783c5
commit
42570efaf8
119
src/stm32f4.c
119
src/stm32f4.c
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@ -23,10 +23,11 @@
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*
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* Refereces:
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* ST doc - RM0090
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* Reference manual - STM32F405xx, STM32F407xx, STM32F415xx/417xx,
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* STM32F42xxx and STM32F43xxx dvanced ARM-based 32-bit MCUs
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* ST doc - RM0368
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* Reference manual - STM32F401xB/C advanced ARM-based 32-bit MCUs
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* Reference manual - STM32F405xx, STM32F407xx, STM32F415xx and STM32F417xx
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* advanced ARM-based 32-bit MCUs
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* ST doc - PM0081
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* Programming manual - STM32F40xxx and STM32F41xxx Flash programming
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* manual
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*/
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#include <stdlib.h>
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@ -90,18 +91,14 @@ static const char stm32f4_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define FLASH_SR (FPEC_BASE+0x0C)
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#define FLASH_CR (FPEC_BASE+0x10)
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#define FLASH_OPTCR (FPEC_BASE+0x14)
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#define FLASH_OPTCR1 (FPEC_BASE+0x18)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_SER (1 << 1)
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_SNB0 (1 << 3)
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#define FLASH_CR_SNB4 (1 << 7)
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#define FLASH_CR_PSIZE8 (0 << 8)
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#define FLASH_CR_PSIZE16 (1 << 8)
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#define FLASH_CR_PSIZE32 (2 << 8)
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#define FLASH_CR_PSIZE64 (3 << 8)
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#define FLASH_CR_MER1 (1 << 15)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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@ -112,12 +109,7 @@ static const char stm32f4_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_DB1M (1 << 30)
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#define FLASH_OPTCR_RESET 0x0fffffed
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#define FLASH_OPTCR_DEFAULT 0x0fffaaed
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#define FLASH_OPTCR_RESET_F4_2_3 0x0ffffffd
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#define FLASH_OPTCR_DEFAULT_F4_2_3 0x0fffaafd
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#define FLASH_OPTCR1_RESET_F4_2_3 0x0fff0000
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#define FLASH_OPTCR_RESERVED 0xf0000013
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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@ -181,7 +173,6 @@ bool stm32f4_probe(struct target_s *target)
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case 0x423: /* F401 */
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case 0x419: /* 427/437 */
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target->driver = stm32f4_driver_str;
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target->idcode = idcode & 0xFFF;
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target->xml_mem_map = stm32f4_xml_memory_map;
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target->flash_erase = stm32f4_flash_erase;
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target->flash_write = stm32f4_flash_write;
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@ -206,54 +197,25 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
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uint16_t sr;
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uint32_t cr;
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uint32_t pagesize;
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int sector;
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int db1m = 0;
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const uint8_t sector2size[] =
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{0x04, 0x04, 0x04, 0x04, 0x10, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20};
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addr &= 0x07FFc000;
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addr &= 0x07FFC000;
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stm32f4_flash_unlock(ap);
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if (target->idcode == 0x419)
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db1m = adiv5_ap_mem_read(ap, FLASH_OPTCR) & FLASH_OPTCR_DB1M;
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while(len) {
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if (addr < 0x10000)
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sector = addr/0x4000; /* Sector 0..3 */
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else if (addr < 0x20000)
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sector = 4;
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else if (!db1m) {
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if (addr < 0x100000) /* Sector 5..11 */
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sector = addr/0x20000 + 4;
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else {
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addr = addr - 0x100000;
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if (addr < 0x10000)
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sector = addr/0x4000 + 12; /* Sector 12..15 */
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else if (addr < 0x20000)
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sector = 16;
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else /* Sector 17..23 */
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sector = addr/0x20000 + 16;
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}
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} else { /* 1MiB device mapped as dual boot */
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if (addr < 0x80000) /* Sector 5..7*/
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sector = addr/0x20000 + 4;
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else {
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addr = addr - 0x80000;
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if (addr < 0x10000)
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sector = addr/0x4000 + 12; /* Sector 12..15 */
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else if (addr < 0x20000)
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sector = 16;
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else /* Sector 17..19 */
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sector = addr/0x20000 + 16;
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}
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if (addr < 0x10000) { /* Sector 0..3 */
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cr = (addr >> 11);
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pagesize = 0x4000;
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} else if (addr < 0x20000) { /* Sector 4 */
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cr = (4 << 3);
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pagesize = 0x10000;
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} else if (addr < 0x100000) { /* Sector 5..11 */
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cr = (((addr - 0x20000) >> 14) + 0x28);
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pagesize = 0x20000;
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} else { /* Sector > 11 ?? */
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return -1;
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}
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cr = FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER;
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if (sector > 11) {
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sector = sector - 12;
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cr |= FLASH_CR_SNB4;
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}
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cr |= (sector) * FLASH_CR_SNB0;
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cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER;
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/* Flash page erase instruction */
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adiv5_ap_mem_write(ap, FLASH_CR, cr);
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/* write address to FMA */
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@ -263,7 +225,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(target))
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return -1;
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pagesize = (sector2size[sector]) << 12;
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len -= pagesize;
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addr += pagesize;
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}
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@ -315,7 +277,6 @@ static bool stm32f4_cmd_erase_mass(target *t)
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{
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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uint32_t flash_cr = FLASH_CR_MER;
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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@ -323,10 +284,9 @@ static bool stm32f4_cmd_erase_mass(target *t)
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stm32f4_flash_unlock(ap);
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/* Flash mass erase start instruction */
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if (t->idcode == 0x419)
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flash_cr |= FLASH_CR_MER1;
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adiv5_ap_mem_write(ap, FLASH_CR, flash_cr);
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adiv5_ap_mem_write(ap, FLASH_CR, flash_cr | FLASH_CR_STRT;
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adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_MER);
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adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER);
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/* Read FLASH_SR to poll for BSY bit */
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) {
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gdb_outf("\b%c", spinner[spinindex++ % 4]);
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@ -345,22 +305,17 @@ static bool stm32f4_cmd_erase_mass(target *t)
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return true;
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}
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static bool stm32f4_option_write(target *t, uint32_t value, uint32_t value1)
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static bool stm32f4_option_write(target *t, uint32_t value)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY1);
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adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY2);
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value &= ~FLASH_OPTCR_RESERVED;
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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if (t->idcode == 0x419) {
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value1 &= FLASH_OPTCR1_RESET_F4_2_3;
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/* WRITE option bytes instruction */
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adiv5_ap_mem_write(ap, FLASH_OPTCR1, value);
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value &= FLASH_OPTCR_RESET_F4_2_3;
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} else
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value &= FLASH_OPTCR_RESET;
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/* WRITE option bytes instruction */
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adiv5_ap_mem_write(ap, FLASH_OPTCR, value);
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adiv5_ap_mem_write(ap, FLASH_OPTCR, value | FLASH_OPTCR_OPTSTRT);
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@ -374,26 +329,19 @@ static bool stm32f4_option_write(target *t, uint32_t value, uint32_t value1)
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static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
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{
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uint32_t addr, val, val1;
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uint32_t addr, val;
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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if ((argc == 2) && !strcmp(argv[1], "erase")) {
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if (t->idcode == 0x419)
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stm32f4_option_write(t, FLASH_OPTCR_DEFAULT_F4_2_3, 0xffffffff);
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else
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stm32f4_option_write(t, FLASH_OPTCR_DEFAULT, 0xffffffff);
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stm32f4_option_write(t, 0x0fffaaed);
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}
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else if ((argc > 2) && !strcmp(argv[1], "write")) {
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else if ((argc == 3) && !strcmp(argv[1], "write")) {
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val = strtoul(argv[2], NULL, 0);
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if (argc > 3)
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val1 = strtoul(argv[3], NULL, 0);
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else
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val1 = 0xffffffff;
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stm32f4_option_write(t, val, val1);
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stm32f4_option_write(t, val);
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} else {
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gdb_out("usage: monitor option erase\n");
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gdb_out("usage: monitor option write <OPTCR> <OPTCR1>\n");
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gdb_out("usage: monitor option write <value>\n");
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}
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for (int i = 0; i < 0xf; i += 8) {
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@ -401,10 +349,5 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
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val = adiv5_ap_mem_read(ap, addr);
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gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF);
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}
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if (t->idcode == 0x419){
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addr = 0x1fffE008;
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val = adiv5_ap_mem_read(ap, addr);
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gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF);
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}
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return true;
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}
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